Struct I2CMasterDma 

pub struct I2CMasterDma<I2C, TX_TRANSFER, RX_TRANSFER>
where
    I2C: Instance,
{ /* private fields */ }

I2c abstraction that can work in non-blocking mode by using DMA

The struct should be used for sending/receiving bytes to/from slave device in non-blocking mode. A client must follow these requirements to use that feature:

• Enable interrupts DMAx_STREAMy used for transmit and another DMAq_STREAMp used for receive.
• In these interrupts call handle_dma_interrupt; defined in trait I2CMasterHandleIT
• Enable interrupts I2Cx_ER for handling errors and call handle_error_interrupt in corresponding handler; defined in trait I2CMasterHandleIT

The struct can be also used to send/receive bytes in blocking mode with methods: write, read, write_read.

Implementations

impl<I2C, TX_TRANSFER, RX_TRANSFER> I2CMasterDma<I2C, TX_TRANSFER, RX_TRANSFER>

where I2C: Instance, TX_TRANSFER: DMATransfer<&'static [u8]>, RX_TRANSFER: DMATransfer<&'static mut [u8]>,

Common implementation

pub fn busy(&self) -> bool

Checks if there is communication in progress

pub fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error>

Reads in blocking mode but if i2c is busy returns WouldBlock and do nothing

pub fn write_read( &mut self, addr: u8, bytes: &[u8], buffer: &mut [u8], ) -> Result<(), Error>

Write and then read in blocking mode but if i2c is busy returns WouldBlock and do nothing

pub fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error>

Write in blocking mode but if i2c is busy returns WouldBlock and do nothing

Trait Implementations

impl<I2C, TX_TRANSFER, RX_TRANSFER> ErrorType for I2CMasterDma<I2C, TX_TRANSFER, RX_TRANSFER>

where I2C: Instance, TX_TRANSFER: DMATransfer<&'static [u8]>, RX_TRANSFER: DMATransfer<&'static mut [u8]>,

type Error = Error

Error type

impl<I2C, RX_STREAM, const RX_CH: u8> I2CMasterHandleIT for I2CMasterDma<I2C, NoDMA, RxDMA<I2C, RX_STREAM, RX_CH>>

where I2C: Instance, RX_STREAM: Stream, ChannelX<RX_CH>: Channel, Rx<I2C>: DMASet<RX_STREAM, RX_CH, PeripheralToMemory>,

fn handle_dma_interrupt(&mut self)

fn handle_error_interrupt(&mut self)

impl<I2C, TX_STREAM, const TX_CH: u8> I2CMasterHandleIT for I2CMasterDma<I2C, TxDMA<I2C, TX_STREAM, TX_CH>, NoDMA>

where I2C: Instance, TX_STREAM: Stream, ChannelX<TX_CH>: Channel, Tx<I2C>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>,

fn handle_dma_interrupt(&mut self)

fn handle_error_interrupt(&mut self)

impl<I2C, TX_STREAM, const TX_CH: u8, RX_STREAM, const RX_CH: u8> I2CMasterHandleIT for I2CMasterDma<I2C, TxDMA<I2C, TX_STREAM, TX_CH>, RxDMA<I2C, RX_STREAM, RX_CH>>

where I2C: Instance, TX_STREAM: Stream, ChannelX<TX_CH>: Channel, Tx<I2C>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>, RX_STREAM: Stream, ChannelX<RX_CH>: Channel, Rx<I2C>: DMASet<RX_STREAM, RX_CH, PeripheralToMemory>,

Only for both TX and RX DMA I2c

fn handle_dma_interrupt(&mut self)

fn handle_error_interrupt(&mut self)

impl<I2C, TX_TRANSFER, RX_STREAM, const RX_CH: u8> I2CMasterReadDMA for I2CMasterDma<I2C, TX_TRANSFER, RxDMA<I2C, RX_STREAM, RX_CH>>

where I2C: Instance, RX_STREAM: Stream, ChannelX<RX_CH>: Channel, Rx<I2C>: DMASet<RX_STREAM, RX_CH, PeripheralToMemory>, TX_TRANSFER: DMATransfer<&'static [u8]>,

unsafe fn read_dma( &mut self, addr: u8, buf: &mut [u8], callback: Option<I2cCompleteCallback>, ) -> Result<(), Error>

Reads bytes from slave device with address addr in non-blocking mode and writes these bytes in buf

impl<I2C, TX_STREAM, const TX_CH: u8, RX_TRANSFER> I2CMasterWriteDMA for I2CMasterDma<I2C, TxDMA<I2C, TX_STREAM, TX_CH>, RX_TRANSFER>

where I2C: Instance, TX_STREAM: Stream, ChannelX<TX_CH>: Channel, Tx<I2C>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>, RX_TRANSFER: DMATransfer<&'static mut [u8]>,

unsafe fn write_dma( &mut self, addr: u8, bytes: &[u8], callback: Option<I2cCompleteCallback>, ) -> Result<(), Error>

Writes bytes to slave with address addr in non-blocking mode

impl<I2C, TX_STREAM, const TX_CH: u8, RX_STREAM, const RX_CH: u8> I2CMasterWriteReadDMA for I2CMasterDma<I2C, TxDMA<I2C, TX_STREAM, TX_CH>, RxDMA<I2C, RX_STREAM, RX_CH>>

where I2C: Instance, TX_STREAM: Stream, ChannelX<TX_CH>: Channel, Tx<I2C>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>, RX_STREAM: Stream, ChannelX<RX_CH>: Channel, Rx<I2C>: DMASet<RX_STREAM, RX_CH, PeripheralToMemory>,

unsafe fn write_read_dma( &mut self, addr: u8, bytes: &[u8], buf: &mut [u8], callback: Option<I2cCompleteCallback>, ) -> Result<(), Error>

Writes bytes to slave with address addr in non-blocking mode and then generate ReStart and receive a bytes from a same device

impl<I2C, TX_TRANSFER, RX_TRANSFER> I2c for I2CMasterDma<I2C, TX_TRANSFER, RX_TRANSFER>

where I2C: Instance, TX_TRANSFER: DMATransfer<&'static [u8]>, RX_TRANSFER: DMATransfer<&'static mut [u8]>,

fn transaction( &mut self, addr: u8, operations: &mut [Operation<'_>], ) -> Result<(), Self::Error>

Execute the provided operations on the I2C bus.

fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>

Reads enough bytes from slave with address to fill read.

fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>

Writes bytes to slave with address address.

fn write_read( &mut self, address: A, write: &[u8], read: &mut [u8], ) -> Result<(), Self::Error>

Writes bytes to slave with address address and then reads enough bytes to fill read in a single transaction.