Struct stm32f4::stm32f413::rcc::pllcfgr::W [−][src]
pub struct W(_);
Expand description
Register PLLCFGR
writer
Implementations
Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks
Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
Bits 16:17 - Main PLL (PLL) division factor for main system clock
Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
Methods from Deref<Target = W<PLLCFGR_SPEC>>
Trait Implementations
Performs the conversion.