Enum stm32f4::stm32f469::rcc::dckcfgr::DSISEL_A

pub enum DSISEL_A {
    DSI_PHY,
    PLLR,
}

DSI clock source selection

Value on reset: 0

Variants

DSI_PHY

0: DSI-PHY used as DSI byte lane clock source (usual case)

PLLR

1: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)

Trait Implementations

impl Clone for DSISEL_A

fn clone(&self) -> DSISEL_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for DSISEL_A

impl Debug for DSISEL_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<DSISEL_A> for bool

fn from(variant: DSISEL_A) -> Self

Performs the conversion.

impl PartialEq<DSISEL_A> for DSISEL_A

fn eq(&self, other: &DSISEL_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for DSISEL_A