stm32f4_staging::stm32f469::dsi::cltcr

Struct CLTCRrs

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pub struct CLTCRrs;
Expand description

DSI Host clock lane timer configuration register

You can read this register and get cltcr::R. You can reset, write, write_with_zero this register using cltcr::W. You can also modify this register. See API.

See register structure

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impl RegisterSpec for CLTCRrs

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type Ux = u32

Raw register type (u8, u16, u32, …).
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impl Resettable for CLTCRrs

reset() method sets CLTCR to value 0

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const RESET_VALUE: Self::Ux = <Self::Ux>::ZERO

Reset value of the register.
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fn reset_value() -> Self::Ux

Reset value of the register.
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impl Writable for CLTCRrs

write(|w| ..) method takes cltcr::W writer structure

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type Safety = Unsafe

Is it safe to write any bits to register
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const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = <Self::Ux>::ZERO

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0
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const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = <Self::Ux>::ZERO

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1
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impl Readable for CLTCRrs

read() method returns cltcr::R reader structure

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