Struct stm32f4_staging::stm32f407::FSMC

pub struct FSMC { /* private fields */ }

Flexible static memory controller

Implementations

impl FSMC

pub const PTR: *const RegisterBlock = {0xa0000000 as *const stm32f407::fsmc::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn bcr1(&self) -> &BCR1

0x00 - SRAM/NOR-Flash chip-select control register 1

pub fn btr(&self, n: usize) -> &BTR

0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s

pub fn btr_iter(&self) -> impl Iterator<Item = &BTR>

Iterator for array of: 0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s

pub fn btr1(&self) -> &BTR

0x04 - SRAM/NOR-Flash chip-select timing register 1

pub fn btr2(&self) -> &BTR

0x0c - SRAM/NOR-Flash chip-select timing register 2

pub fn btr3(&self) -> &BTR

0x14 - SRAM/NOR-Flash chip-select timing register 3

pub fn btr4(&self) -> &BTR

0x1c - SRAM/NOR-Flash chip-select timing register 4

pub fn bcr(&self, n: usize) -> &BCR

0x08..0x14 - SRAM/NOR-Flash chip-select control register %s

pub fn bcr_iter(&self) -> impl Iterator<Item = &BCR>

Iterator for array of: 0x08..0x14 - SRAM/NOR-Flash chip-select control register %s

pub fn bcr2(&self) -> &BCR

0x08 - SRAM/NOR-Flash chip-select control register 2

pub fn bcr3(&self) -> &BCR

0x10 - SRAM/NOR-Flash chip-select control register 3

pub fn bcr4(&self) -> &BCR

0x18 - SRAM/NOR-Flash chip-select control register 4

pub fn pcr(&self, n: usize) -> &PCR

0x60..0x6c - PC Card/NAND Flash control register %s

pub fn pcr_iter(&self) -> impl Iterator<Item = &PCR>

Iterator for array of: 0x60..0x6c - PC Card/NAND Flash control register %s

pub fn pcr2(&self) -> &PCR

0x60 - PC Card/NAND Flash control register 2

pub fn pcr3(&self) -> &PCR

0x80 - PC Card/NAND Flash control register 3

pub fn pcr4(&self) -> &PCR

0xa0 - PC Card/NAND Flash control register 4

pub fn sr(&self, n: usize) -> &SR

0x64..0x70 - FIFO status and interrupt register %s

pub fn sr_iter(&self) -> impl Iterator<Item = &SR>

Iterator for array of: 0x64..0x70 - FIFO status and interrupt register %s

pub fn sr2(&self) -> &SR

0x64 - FIFO status and interrupt register 2

pub fn sr3(&self) -> &SR

0x84 - FIFO status and interrupt register 3

pub fn sr4(&self) -> &SR

0xa4 - FIFO status and interrupt register 4

pub fn pmem2(&self) -> &PMEM2

0x68 - Common memory space timing register 2

pub fn patt2(&self) -> &PATT2

0x6c - Attribute memory space timing register 2

pub fn eccr2(&self) -> &ECCR2

0x74 - ECC result register 2

pub fn pmem3(&self) -> &PMEM3

0x88 - Common memory space timing register 3

pub fn patt3(&self) -> &PATT3

0x8c - Attribute memory space timing register 3

pub fn eccr3(&self) -> &ECCR3

0x94 - ECC result register 3

pub fn pmem4(&self) -> &PMEM4

0xa8 - Common memory space timing register 4

pub fn patt4(&self) -> &PATT4

0xac - Attribute memory space timing register 4

pub fn pio4(&self) -> &PIO4

0xb0 - I/O space timing register 4

pub fn bwtr(&self, n: usize) -> &BWTR

0x104..0x114 - SRAM/NOR-Flash write timing registers %s

pub fn bwtr_iter(&self) -> impl Iterator<Item = &BWTR>

Iterator for array of: 0x104..0x114 - SRAM/NOR-Flash write timing registers %s

pub fn bwtr1(&self) -> &BWTR

0x104 - SRAM/NOR-Flash write timing registers 1

pub fn bwtr2(&self) -> &BWTR

0x10c - SRAM/NOR-Flash write timing registers 2

pub fn bwtr3(&self) -> &BWTR

0x114 - SRAM/NOR-Flash write timing registers 3

pub fn bwtr4(&self) -> &BWTR

0x11c - SRAM/NOR-Flash write timing registers 4

Trait Implementations

impl Debug for FSMC

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for FSMC

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for FSMC