Struct stm32f1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _BCR1>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low Power Deep Sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power Down Deep Sleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear Wake-up Flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear STANDBY Flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power Voltage Detector Enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD Level Selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable Backup Domain write protection

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB High speed prescaler (APB2)

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 14:15 - ADC prescaler

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn afiorst(&mut self) -> AFIORST_W<'_>

Bit 0 - Alternate function I/O reset

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 2 - IO port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 3 - IO port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 4 - IO port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 5 - IO port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 6 - IO port E reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 7 - IO port F reset

pub fn iopgrst(&mut self) -> IOPGRST_W<'_>

Bit 8 - IO port G reset

pub fn adc1rst(&mut self) -> ADC1RST_W<'_>

Bit 9 - ADC 1 interface reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - Timer 5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - Timer 12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - Timer 13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - Timer 14 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - USART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - USART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn bkprst(&mut self) -> BKPRST_W<'_>

Bit 27 - Backup interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC interface reset

pub fn cecrst(&mut self) -> CECRST_W<'_>

Bit 30 - CEC reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn fsmcen(&mut self) -> FSMCEN_W<'_>

Bit 8 - FSMC clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn afioen(&mut self) -> AFIOEN_W<'_>

Bit 0 - Alternate function I/O clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 2 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 3 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 4 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 5 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 6 - I/O port E clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 7 - I/O port F clock enable

pub fn iopgen(&mut self) -> IOPGEN_W<'_>

Bit 8 - I/O port G clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 9 - ADC 1 interface clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 Timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 Timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 Timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM17 Timer clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - Timer 5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - Timer 12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - Timer 13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - Timer 14 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART 4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART 5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn bkpen(&mut self) -> BKPEN_W<'_>

Bit 27 - Backup interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC interface clock enable

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 30 - CEC clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CFGR2>>

pub fn prediv1(&mut self) -> PREDIV1_W<'_>

Bits 0:3 - PREDIV1 division factor

impl W<u32, Reg<u32, _CRL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:1 - Port n.0 mode bits

pub fn cnf0(&mut self) -> CNF0_W<'_>

Bits 2:3 - Port n.0 configuration bits

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:5 - Port n.1 mode bits

pub fn cnf1(&mut self) -> CNF1_W<'_>

Bits 6:7 - Port n.1 configuration bits

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:9 - Port n.2 mode bits

pub fn cnf2(&mut self) -> CNF2_W<'_>

Bits 10:11 - Port n.2 configuration bits

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:13 - Port n.3 mode bits

pub fn cnf3(&mut self) -> CNF3_W<'_>

Bits 14:15 - Port n.3 configuration bits

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:17 - Port n.4 mode bits

pub fn cnf4(&mut self) -> CNF4_W<'_>

Bits 18:19 - Port n.4 configuration bits

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:21 - Port n.5 mode bits

pub fn cnf5(&mut self) -> CNF5_W<'_>

Bits 22:23 - Port n.5 configuration bits

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:25 - Port n.6 mode bits

pub fn cnf6(&mut self) -> CNF6_W<'_>

Bits 26:27 - Port n.6 configuration bits

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:29 - Port n.7 mode bits

pub fn cnf7(&mut self) -> CNF7_W<'_>

Bits 30:31 - Port n.7 configuration bits

impl W<u32, Reg<u32, _CRH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:1 - Port n.8 mode bits

pub fn cnf8(&mut self) -> CNF8_W<'_>

Bits 2:3 - Port n.8 configuration bits

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:5 - Port n.9 mode bits

pub fn cnf9(&mut self) -> CNF9_W<'_>

Bits 6:7 - Port n.9 configuration bits

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:9 - Port n.10 mode bits

pub fn cnf10(&mut self) -> CNF10_W<'_>

Bits 10:11 - Port n.10 configuration bits

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:13 - Port n.11 mode bits

pub fn cnf11(&mut self) -> CNF11_W<'_>

Bits 14:15 - Port n.11 configuration bits

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:17 - Port n.12 mode bits

pub fn cnf12(&mut self) -> CNF12_W<'_>

Bits 18:19 - Port n.12 configuration bits

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:21 - Port n.13 mode bits

pub fn cnf13(&mut self) -> CNF13_W<'_>

Bits 22:23 - Port n.13 configuration bits

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:25 - Port n.14 mode bits

pub fn cnf14(&mut self) -> CNF14_W<'_>

Bits 26:27 - Port n.14 configuration bits

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:29 - Port n.15 mode bits

pub fn cnf15(&mut self) -> CNF15_W<'_>

Bits 30:31 - Port n.15 configuration bits

impl W<u32, Reg<u32, _ODR>>

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data

impl W<u32, Reg<u32, _BSRR>>

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Set bit 0

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Set bit 1

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Set bit 1

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Set bit 3

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Set bit 4

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Set bit 5

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Set bit 6

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Set bit 7

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Set bit 8

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Set bit 9

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Set bit 10

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Set bit 11

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Set bit 12

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Set bit 13

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Set bit 14

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Set bit 15

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Reset bit 15

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Reset bit 1

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Reset bit 15

impl W<u32, Reg<u32, _LCKR>>

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port A Lock bit 0

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port A Lock bit 1

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port A Lock bit 2

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port A Lock bit 3

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port A Lock bit 4

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port A Lock bit 5

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port A Lock bit 6

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port A Lock bit 7

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port A Lock bit 8

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port A Lock bit 9

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port A Lock bit 10

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port A Lock bit 11

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port A Lock bit 12

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port A Lock bit 13

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port A Lock bit 14

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port A Lock bit 15

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lock key

impl W<u32, Reg<u32, _EVCR>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:3 - Pin selection

pub fn port(&mut self) -> PORT_W<'_>

Bits 4:6 - Port selection

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 7 - Event Output Enable

impl W<u32, Reg<u32, _MAPR>>

pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<'_>

Bit 0 - SPI1 remapping

pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<'_>

Bit 1 - I2C1 remapping

pub fn usart1_remap(&mut self) -> USART1_REMAP_W<'_>

Bit 2 - USART1 remapping

pub fn usart2_remap(&mut self) -> USART2_REMAP_W<'_>

Bit 3 - USART2 remapping

pub fn usart3_remap(&mut self) -> USART3_REMAP_W<'_>

Bits 4:5 - USART3 remapping

pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<'_>

Bits 6:7 - TIM1 remapping

pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<'_>

Bits 8:9 - TIM2 remapping

pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<'_>

Bits 10:11 - TIM3 remapping

pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<'_>

Bit 12 - TIM4 remapping

pub fn pd01_remap(&mut self) -> PD01_REMAP_W<'_>

Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT

pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<'_>

Bit 16 - Set and cleared by software

pub fn swj_cfg(&mut self) -> SWJ_CFG_W<'_>

Bits 24:26 - Serial wire JTAG configuration

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI0 configuration

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI1 configuration

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI2 configuration

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI3 configuration

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI4 configuration

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI5 configuration

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI6 configuration

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI7 configuration

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI8 configuration

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI9 configuration

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10 configuration

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI11 configuration

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI12 configuration

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI13 configuration

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI14 configuration

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI15 configuration

impl W<u32, Reg<u32, _MAPR2>>

pub fn tim15_remap(&mut self) -> TIM15_REMAP_W<'_>

Bit 0 - TIM15 remapping

pub fn tim16_remap(&mut self) -> TIM16_REMAP_W<'_>

Bit 1 - TIM16 remapping

pub fn tim17_remap(&mut self) -> TIM17_REMAP_W<'_>

Bit 2 - TIM17 remapping

pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<'_>

Bit 8 - TIM13 remapping

pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<'_>

Bit 9 - TIM14 remapping

pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<'_>

Bit 10 - NADV connect/disconnect

pub fn cec_remap(&mut self) -> CEC_REMAP_W<'_>

Bit 3 - CEC remapping

pub fn tim1_dma_remap(&mut self) -> TIM1_DMA_REMAP_W<'_>

Bit 4 - TIM1 DMA remapping

pub fn tim67_dac_dma_remap(&mut self) -> TIM67_DAC_DMA_REMAP_W<'_>

Bit 11 - TIM67_DAC DMA remapping

pub fn tim12_remap(&mut self) -> TIM12_REMAP_W<'_>

Bit 12 - TIM12 remapping

pub fn misc_remap(&mut self) -> MISC_REMAP_W<'_>

Bit 13 - Miscellaneous features remapping

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CRH>>

pub fn secie(&mut self) -> SECIE_W<'_>

Bit 0 - Second interrupt Enable

pub fn alrie(&mut self) -> ALRIE_W<'_>

Bit 1 - Alarm interrupt Enable

pub fn owie(&mut self) -> OWIE_W<'_>

Bit 2 - Overflow interrupt Enable

impl W<u32, Reg<u32, _CRL>>

pub fn secf(&mut self) -> SECF_W<'_>

Bit 0 - Second Flag

pub fn alrf(&mut self) -> ALRF_W<'_>

Bit 1 - Alarm Flag

pub fn owf(&mut self) -> OWF_W<'_>

Bit 2 - Overflow Flag

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 3 - Registers Synchronized Flag

pub fn cnf(&mut self) -> CNF_W<'_>

Bit 4 - Configuration Flag

impl W<u32, Reg<u32, _PRLH>>

pub fn prlh(&mut self) -> PRLH_W<'_>

Bits 0:3 - RTC Prescaler Load Register High

impl W<u32, Reg<u32, _PRLL>>

pub fn prll(&mut self) -> PRLL_W<'_>

Bits 0:15 - RTC Prescaler Divider Register Low

impl W<u32, Reg<u32, _CNTH>>

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 0:15 - RTC counter register high

impl W<u32, Reg<u32, _CNTL>>

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 0:15 - RTC counter register Low

impl W<u32, Reg<u32, _ALRH>>

pub fn alrh(&mut self) -> ALRH_W<'_>

Bits 0:15 - RTC alarm register high

impl W<u32, Reg<u32, _ALRL>>

pub fn alrl(&mut self) -> ALRL_W<'_>

Bits 0:15 - RTC alarm register low

impl W<u32, Reg<u32, _DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _BKP_DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _RTCCR>>

pub fn cal(&mut self) -> CAL_W<'_>

Bits 0:6 - Calibration value

pub fn cco(&mut self) -> CCO_W<'_>

Bit 7 - Calibration Clock Output

pub fn asoe(&mut self) -> ASOE_W<'_>

Bit 8 - Alarm or second output enable

pub fn asos(&mut self) -> ASOS_W<'_>

Bit 9 - Alarm or second output selection

impl W<u32, Reg<u32, _CR>>

pub fn tpe(&mut self) -> TPE_W<'_>

Bit 0 - Tamper pin enable

pub fn tpal(&mut self) -> TPAL_W<'_>

Bit 1 - Tamper pin active level

impl W<u32, Reg<u32, _CSR>>

pub fn cte(&mut self) -> CTE_W<'_>

Bit 0 - Clear Tamper event

pub fn cti(&mut self) -> CTI_W<'_>

Bit 1 - Clear Tamper Interrupt

pub fn tpie(&mut self) -> TPIE_W<'_>

Bit 2 - Tamper Pin interrupt enable

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

impl W<u32, Reg<u32, _CFR>>

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early Wakeup Interrupt

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer Base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early Wakeup Interrupt

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 15:18 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 15:18 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel 1

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel 2

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel 3

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel 4

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA underrun interrupt enable

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 8 - DBG_IWDG_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 9 - DBG_WWDG_STOP

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 10 - DBG_TIM1_STOP

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 11 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 12 - DBG_TIM3_STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 13 - DBG_TIM4_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 15 - DBG_I2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 16 - DBG_I2C2_SMBUS_TIMEOUT

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 18 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 19 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 20 - DBG_TIM7_STOP

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 22 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 23 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 24 - DBG_TIM17_STOP

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 25 - DBG_TIM12_STOP

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 26 - DBG_TIM13_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 27 - DBG_TIM14_STOP

impl W<u32, Reg<u32, _SR>>

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - DR

impl W<u32, Reg<u32, _BRR>>

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - DIV_Fraction

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - DIV_Mantissa

impl W<u32, Reg<u32, _CR1>>

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Reset bit

impl W<u32, Reg<u32, _ACR>>

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash Address

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CFGR>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn ie(&mut self) -> IE_W<'_>

Bit 1 - Interrupt enable

pub fn btem(&mut self) -> BTEM_W<'_>

Bit 2 - Bit timing error mode

pub fn bpem(&mut self) -> BPEM_W<'_>

Bit 3 - Bit period error mode

impl W<u32, Reg<u32, _OAR>>

pub fn oa(&mut self) -> OA_W<'_>

Bits 0:3 - Own address

impl W<u32, Reg<u32, _PRES>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 0:13 - CEC Rx Data Register

impl W<u32, Reg<u32, _CSR>>

pub fn tsom(&mut self) -> TSOM_W<'_>

Bit 0 - Tx start of message

pub fn teom(&mut self) -> TEOM_W<'_>

Bit 1 - Tx end of message

pub fn terr(&mut self) -> TERR_W<'_>

Bit 2 - Tx error

pub fn tbtrf(&mut self) -> TBTRF_W<'_>

Bit 3 - Tx byte transfer request or block transfer finished

pub fn rsom(&mut self) -> RSOM_W<'_>

Bit 4 - Rx start of message

pub fn reom(&mut self) -> REOM_W<'_>

Bit 5 - Rx end of message

pub fn rerr(&mut self) -> RERR_W<'_>

Bit 6 - Rx error

pub fn rbtf(&mut self) -> RBTF_W<'_>

Bit 7 - Rx byte/block transfer finished

impl W<u32, Reg<u32, _TXD>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - Tx Data register

impl W<u32, Reg<u32, _ACTRL>>

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD_>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

impl W<u32, Reg<u32, _BCR1>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR2>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR2>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM2>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT2>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - Attribute memory x databus HiZ time

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - Attribute memory x hold time

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - Attribute memory x wait time

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - Attribute memory x setup time

impl W<u32, Reg<u32, _PCR3>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR3>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM3>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT3>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR4>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR4>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM4>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT4>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PIO4>>

pub fn iohizx(&mut self) -> IOHIZX_W<'_>

Bits 24:31 - IOHIZx

pub fn ioholdx(&mut self) -> IOHOLDX_W<'_>

Bits 16:23 - IOHOLDx

pub fn iowaitx(&mut self) -> IOWAITX_W<'_>

Bits 8:15 - IOWAITx

pub fn iosetx(&mut self) -> IOSETX_W<'_>

Bits 0:7 - IOSETx

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low Power Deep Sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power Down Deep Sleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear Wake-up Flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear STANDBY Flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power Voltage Detector Enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD Level Selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable Backup Domain write protection

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB High speed prescaler (APB2)

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 14:15 - ADC prescaler

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn afiorst(&mut self) -> AFIORST_W<'_>

Bit 0 - Alternate function I/O reset

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 2 - IO port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 3 - IO port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 4 - IO port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 5 - IO port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 6 - IO port E reset

pub fn adc1rst(&mut self) -> ADC1RST_W<'_>

Bit 9 - ADC 1 interface reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>

Bit 19 - TIM9 timer reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>

Bit 20 - TIM10 timer reset

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>

Bit 21 - TIM11 timer reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 7 - IO port F reset

pub fn iopgrst(&mut self) -> IOPGRST_W<'_>

Bit 8 - IO port G reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - Timer 5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - Timer 12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - Timer 13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - Timer 14 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - UART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - UART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn bkprst(&mut self) -> BKPRST_W<'_>

Bit 27 - Backup interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC interface reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn fsmcen(&mut self) -> FSMCEN_W<'_>

Bit 8 - FSMC clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn afioen(&mut self) -> AFIOEN_W<'_>

Bit 0 - Alternate function I/O clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 2 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 3 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 4 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 5 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 6 - I/O port E clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 7 - I/O port F clock enable

pub fn iopgen(&mut self) -> IOPGEN_W<'_>

Bit 8 - I/O port G clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 9 - ADC 1 interface clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>

Bit 19 - TIM9 Timer clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>

Bit 20 - TIM10 Timer clock enable

pub fn tim11en(&mut self) -> TIM11EN_W<'_>

Bit 21 - TIM11 Timer clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - Timer 5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - Timer 12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - Timer 13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - Timer 14 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART 4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART 5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn bkpen(&mut self) -> BKPEN_W<'_>

Bit 27 - Backup interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC interface clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CRL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:1 - Port n.0 mode bits

pub fn cnf0(&mut self) -> CNF0_W<'_>

Bits 2:3 - Port n.0 configuration bits

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:5 - Port n.1 mode bits

pub fn cnf1(&mut self) -> CNF1_W<'_>

Bits 6:7 - Port n.1 configuration bits

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:9 - Port n.2 mode bits

pub fn cnf2(&mut self) -> CNF2_W<'_>

Bits 10:11 - Port n.2 configuration bits

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:13 - Port n.3 mode bits

pub fn cnf3(&mut self) -> CNF3_W<'_>

Bits 14:15 - Port n.3 configuration bits

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:17 - Port n.4 mode bits

pub fn cnf4(&mut self) -> CNF4_W<'_>

Bits 18:19 - Port n.4 configuration bits

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:21 - Port n.5 mode bits

pub fn cnf5(&mut self) -> CNF5_W<'_>

Bits 22:23 - Port n.5 configuration bits

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:25 - Port n.6 mode bits

pub fn cnf6(&mut self) -> CNF6_W<'_>

Bits 26:27 - Port n.6 configuration bits

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:29 - Port n.7 mode bits

pub fn cnf7(&mut self) -> CNF7_W<'_>

Bits 30:31 - Port n.7 configuration bits

impl W<u32, Reg<u32, _CRH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:1 - Port n.8 mode bits

pub fn cnf8(&mut self) -> CNF8_W<'_>

Bits 2:3 - Port n.8 configuration bits

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:5 - Port n.9 mode bits

pub fn cnf9(&mut self) -> CNF9_W<'_>

Bits 6:7 - Port n.9 configuration bits

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:9 - Port n.10 mode bits

pub fn cnf10(&mut self) -> CNF10_W<'_>

Bits 10:11 - Port n.10 configuration bits

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:13 - Port n.11 mode bits

pub fn cnf11(&mut self) -> CNF11_W<'_>

Bits 14:15 - Port n.11 configuration bits

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:17 - Port n.12 mode bits

pub fn cnf12(&mut self) -> CNF12_W<'_>

Bits 18:19 - Port n.12 configuration bits

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:21 - Port n.13 mode bits

pub fn cnf13(&mut self) -> CNF13_W<'_>

Bits 22:23 - Port n.13 configuration bits

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:25 - Port n.14 mode bits

pub fn cnf14(&mut self) -> CNF14_W<'_>

Bits 26:27 - Port n.14 configuration bits

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:29 - Port n.15 mode bits

pub fn cnf15(&mut self) -> CNF15_W<'_>

Bits 30:31 - Port n.15 configuration bits

impl W<u32, Reg<u32, _ODR>>

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data

impl W<u32, Reg<u32, _BSRR>>

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Set bit 0

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Set bit 1

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Set bit 1

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Set bit 3

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Set bit 4

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Set bit 5

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Set bit 6

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Set bit 7

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Set bit 8

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Set bit 9

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Set bit 10

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Set bit 11

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Set bit 12

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Set bit 13

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Set bit 14

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Set bit 15

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Reset bit 15

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Reset bit 1

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Reset bit 15

impl W<u32, Reg<u32, _LCKR>>

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port A Lock bit 0

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port A Lock bit 1

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port A Lock bit 2

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port A Lock bit 3

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port A Lock bit 4

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port A Lock bit 5

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port A Lock bit 6

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port A Lock bit 7

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port A Lock bit 8

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port A Lock bit 9

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port A Lock bit 10

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port A Lock bit 11

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port A Lock bit 12

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port A Lock bit 13

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port A Lock bit 14

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port A Lock bit 15

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lock key

impl W<u32, Reg<u32, _EVCR>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:3 - Pin selection

pub fn port(&mut self) -> PORT_W<'_>

Bits 4:6 - Port selection

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 7 - Event Output Enable

impl W<u32, Reg<u32, _MAPR>>

pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<'_>

Bit 0 - SPI1 remapping

pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<'_>

Bit 1 - I2C1 remapping

pub fn usart1_remap(&mut self) -> USART1_REMAP_W<'_>

Bit 2 - USART1 remapping

pub fn usart2_remap(&mut self) -> USART2_REMAP_W<'_>

Bit 3 - USART2 remapping

pub fn usart3_remap(&mut self) -> USART3_REMAP_W<'_>

Bits 4:5 - USART3 remapping

pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<'_>

Bits 6:7 - TIM1 remapping

pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<'_>

Bits 8:9 - TIM2 remapping

pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<'_>

Bits 10:11 - TIM3 remapping

pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<'_>

Bit 12 - TIM4 remapping

pub fn can_remap(&mut self) -> CAN_REMAP_W<'_>

Bits 13:14 - CAN1 remapping

pub fn pd01_remap(&mut self) -> PD01_REMAP_W<'_>

Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT

pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<'_>

Bit 16 - Set and cleared by software

pub fn adc1_etrginj_remap(&mut self) -> ADC1_ETRGINJ_REMAP_W<'_>

Bit 17 - ADC 1 External trigger injected conversion remapping

pub fn adc1_etrgreg_remap(&mut self) -> ADC1_ETRGREG_REMAP_W<'_>

Bit 18 - ADC 1 external trigger regular conversion remapping

pub fn adc2_etrginj_remap(&mut self) -> ADC2_ETRGINJ_REMAP_W<'_>

Bit 19 - ADC 2 external trigger injected conversion remapping

pub fn adc2_etrgreg_remap(&mut self) -> ADC2_ETRGREG_REMAP_W<'_>

Bit 20 - ADC 2 external trigger regular conversion remapping

pub fn swj_cfg(&mut self) -> SWJ_CFG_W<'_>

Bits 24:26 - Serial wire JTAG configuration

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI0 configuration

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI1 configuration

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI2 configuration

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI3 configuration

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI4 configuration

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI5 configuration

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI6 configuration

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI7 configuration

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI8 configuration

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI9 configuration

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10 configuration

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI11 configuration

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI12 configuration

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI13 configuration

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI14 configuration

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI15 configuration

impl W<u32, Reg<u32, _MAPR2>>

pub fn tim9_remap(&mut self) -> TIM9_REMAP_W<'_>

Bit 5 - TIM9 remapping

pub fn tim10_remap(&mut self) -> TIM10_REMAP_W<'_>

Bit 6 - TIM10 remapping

pub fn tim11_remap(&mut self) -> TIM11_REMAP_W<'_>

Bit 7 - TIM11 remapping

pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<'_>

Bit 8 - TIM13 remapping

pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<'_>

Bit 9 - TIM14 remapping

pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<'_>

Bit 10 - NADV connect/disconnect

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CRH>>

pub fn secie(&mut self) -> SECIE_W<'_>

Bit 0 - Second interrupt Enable

pub fn alrie(&mut self) -> ALRIE_W<'_>

Bit 1 - Alarm interrupt Enable

pub fn owie(&mut self) -> OWIE_W<'_>

Bit 2 - Overflow interrupt Enable

impl W<u32, Reg<u32, _CRL>>

pub fn secf(&mut self) -> SECF_W<'_>

Bit 0 - Second Flag

pub fn alrf(&mut self) -> ALRF_W<'_>

Bit 1 - Alarm Flag

pub fn owf(&mut self) -> OWF_W<'_>

Bit 2 - Overflow Flag

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 3 - Registers Synchronized Flag

pub fn cnf(&mut self) -> CNF_W<'_>

Bit 4 - Configuration Flag

impl W<u32, Reg<u32, _PRLH>>

pub fn prlh(&mut self) -> PRLH_W<'_>

Bits 0:3 - RTC Prescaler Load Register High

impl W<u32, Reg<u32, _PRLL>>

pub fn prll(&mut self) -> PRLL_W<'_>

Bits 0:15 - RTC Prescaler Divider Register Low

impl W<u32, Reg<u32, _CNTH>>

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 0:15 - RTC counter register high

impl W<u32, Reg<u32, _CNTL>>

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 0:15 - RTC counter register Low

impl W<u32, Reg<u32, _ALRH>>

pub fn alrh(&mut self) -> ALRH_W<'_>

Bits 0:15 - RTC alarm register high

impl W<u32, Reg<u32, _ALRL>>

pub fn alrl(&mut self) -> ALRL_W<'_>

Bits 0:15 - RTC alarm register low

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

impl W<u32, Reg<u32, _CFR>>

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early Wakeup Interrupt

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer Base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early Wakeup Interrupt

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 8 - DBG_IWDG_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 9 - DBG_WWDG_STOP

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 10 - DBG_TIM1_STOP

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 11 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 12 - DBG_TIM3_STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 13 - DBG_TIM4_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 15 - DBG_I2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 16 - DBG_I2C2_SMBUS_TIMEOUT

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 18 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 19 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 20 - DBG_TIM7_STOP

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 22 - TIM15 counter stopped when core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 23 - TIM16 counter stopped when core is halted

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 24 - TIM17 counter stopped when core is halted

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 25 - TIM12 counter stopped when core is halted

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 26 - TIM13 counter stopped when core is halted

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 27 - TIM14 counter stopped when core is halted

impl W<u32, Reg<u32, _SR>>

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - DR

impl W<u32, Reg<u32, _BRR>>

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - DIV_Fraction

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - DIV_Mantissa

impl W<u32, Reg<u32, _CR1>>

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Reset bit

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - Prefetch buffer enable

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash Address

impl W<u32, Reg<u32, _DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _BKP_DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _RTCCR>>

pub fn cal(&mut self) -> CAL_W<'_>

Bits 0:6 - Calibration value

pub fn cco(&mut self) -> CCO_W<'_>

Bit 7 - Calibration Clock Output

pub fn asoe(&mut self) -> ASOE_W<'_>

Bit 8 - Alarm or second output enable

pub fn asos(&mut self) -> ASOS_W<'_>

Bit 9 - Alarm or second output selection

impl W<u32, Reg<u32, _CR>>

pub fn tpe(&mut self) -> TPE_W<'_>

Bit 0 - Tamper pin enable

pub fn tpal(&mut self) -> TPAL_W<'_>

Bit 1 - Tamper pin active level

impl W<u32, Reg<u32, _CSR>>

pub fn cte(&mut self) -> CTE_W<'_>

Bit 0 - Clear Tamper event

pub fn cti(&mut self) -> CTI_W<'_>

Bit 1 - Clear Tamper Interrupt

pub fn tpie(&mut self) -> TPIE_W<'_>

Bit 2 - Tamper Pin interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn dualmod(&mut self) -> DUALMOD_W<'_>

Bits 16:19 - Dual mode selection

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _FS_DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _FS_DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _FS_DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _FS_DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _FS_DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _FS_DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _FS_GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _FS_GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _FS_GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _FS_GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _FS_GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _FS_GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _FS_GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _FS_GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_DEVICE>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _FS_CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _FS_HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _FS_HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _FS_HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _FS_HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _MMCCR>>

pub fn cr(&mut self) -> CR_W<'_>

Bit 0 - Counter reset

pub fn csr(&mut self) -> CSR_W<'_>

Bit 1 - Counter stop rollover

pub fn ror(&mut self) -> ROR_W<'_>

Bit 2 - Reset on read

pub fn mcf(&mut self) -> MCF_W<'_>

Bit 31 - MMC counter freeze

impl W<u32, Reg<u32, _MMCRIR>>

pub fn rfces(&mut self) -> RFCES_W<'_>

Bit 5 - Received frames CRC error status

pub fn rfaes(&mut self) -> RFAES_W<'_>

Bit 6 - Received frames alignment error status

pub fn rgufs(&mut self) -> RGUFS_W<'_>

Bit 17 - Received Good Unicast Frames Status

impl W<u32, Reg<u32, _MMCTIR>>

pub fn tgfscs(&mut self) -> TGFSCS_W<'_>

Bit 14 - Transmitted good frames single collision status

pub fn tgfmscs(&mut self) -> TGFMSCS_W<'_>

Bit 15 - Transmitted good frames more single collision status

pub fn tgfs(&mut self) -> TGFS_W<'_>

Bit 21 - Transmitted good frames status

impl W<u32, Reg<u32, _MMCRIMR>>

pub fn rfcem(&mut self) -> RFCEM_W<'_>

Bit 5 - Received frame CRC error mask

pub fn rfaem(&mut self) -> RFAEM_W<'_>

Bit 6 - Received frames alignment error mask

pub fn rgufm(&mut self) -> RGUFM_W<'_>

Bit 17 - Received good unicast frames mask

impl W<u32, Reg<u32, _MMCTIMR>>

pub fn tgfscm(&mut self) -> TGFSCM_W<'_>

Bit 14 - Transmitted good frames single collision mask

pub fn tgfmscm(&mut self) -> TGFMSCM_W<'_>

Bit 15 - Transmitted good frames more single collision mask

pub fn tgfm(&mut self) -> TGFM_W<'_>

Bit 21 - Transmitted good frames mask

impl W<u32, Reg<u32, _MACCR>>

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn dc(&mut self) -> DC_W<'_>

Bit 4 - Deferral check

pub fn bl(&mut self) -> BL_W<'_>

Bits 5:6 - Back-off limit

pub fn apcs(&mut self) -> APCS_W<'_>

Bit 7 - Automatic pad/CRC stripping

pub fn rd(&mut self) -> RD_W<'_>

Bit 9 - Retry disable

pub fn ipco(&mut self) -> IPCO_W<'_>

Bit 10 - IPv4 checksum offload

pub fn dm(&mut self) -> DM_W<'_>

Bit 11 - Duplex mode

pub fn lm(&mut self) -> LM_W<'_>

Bit 12 - Loopback mode

pub fn rod(&mut self) -> ROD_W<'_>

Bit 13 - Receive own disable

pub fn fes(&mut self) -> FES_W<'_>

Bit 14 - Fast Ethernet speed

pub fn csd(&mut self) -> CSD_W<'_>

Bit 16 - Carrier sense disable

pub fn ifg(&mut self) -> IFG_W<'_>

Bits 17:19 - Interframe gap

pub fn jd(&mut self) -> JD_W<'_>

Bit 22 - Jabber disable

pub fn wd(&mut self) -> WD_W<'_>

Bit 23 - Watchdog disable

impl W<u32, Reg<u32, _MACFFR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 0 - Promiscuous mode

pub fn hu(&mut self) -> HU_W<'_>

Bit 1 - Hash unicast

pub fn hm(&mut self) -> HM_W<'_>

Bit 2 - Hash multicast

pub fn daif(&mut self) -> DAIF_W<'_>

Bit 3 - Destination address inverse filtering

pub fn pam(&mut self) -> PAM_W<'_>

Bit 4 - Pass all multicast

pub fn bfd(&mut self) -> BFD_W<'_>

Bit 5 - Broadcast frames disable

pub fn pcf(&mut self) -> PCF_W<'_>

Bits 6:7 - Pass control frames

pub fn saif(&mut self) -> SAIF_W<'_>

Bit 8 - Source address inverse filtering

pub fn saf(&mut self) -> SAF_W<'_>

Bit 9 - Source address filter

pub fn hpf(&mut self) -> HPF_W<'_>

Bit 10 - Hash or perfect filter

pub fn ra(&mut self) -> RA_W<'_>

Bit 31 - Receive all

impl W<u32, Reg<u32, _MACHTHR>>

pub fn hth(&mut self) -> HTH_W<'_>

Bits 0:31 - Hash table high

impl W<u32, Reg<u32, _MACHTLR>>

pub fn htl(&mut self) -> HTL_W<'_>

Bits 0:31 - Hash table low

impl W<u32, Reg<u32, _MACMIIAR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - MII busy

pub fn mw(&mut self) -> MW_W<'_>

Bit 1 - MII write

pub fn cr(&mut self) -> CR_W<'_>

Bits 2:4 - Clock range

pub fn mr(&mut self) -> MR_W<'_>

Bits 6:10 - MII register

pub fn pa(&mut self) -> PA_W<'_>

Bits 11:15 - PHY address

impl W<u32, Reg<u32, _MACMIIDR>>

pub fn md(&mut self) -> MD_W<'_>

Bits 0:15 - MII data

impl W<u32, Reg<u32, _MACFCR>>

pub fn fcb_bpa(&mut self) -> FCB_BPA_W<'_>

Bit 0 - Flow control busy/back pressure activate

pub fn tfce(&mut self) -> TFCE_W<'_>

Bit 1 - Transmit flow control enable

pub fn rfce(&mut self) -> RFCE_W<'_>

Bit 2 - Receive flow control enable

pub fn upfd(&mut self) -> UPFD_W<'_>

Bit 3 - Unicast pause frame detect

pub fn plt(&mut self) -> PLT_W<'_>

Bits 4:5 - Pause low threshold

pub fn zqpd(&mut self) -> ZQPD_W<'_>

Bit 7 - Zero-quanta pause disable

pub fn pt(&mut self) -> PT_W<'_>

Bits 16:31 - Pass control frames

impl W<u32, Reg<u32, _MACVLANTR>>

pub fn vlanti(&mut self) -> VLANTI_W<'_>

Bits 0:15 - VLAN tag identifier (for receive frames)

pub fn vlantc(&mut self) -> VLANTC_W<'_>

Bit 16 - 12-bit VLAN tag comparison

impl W<u32, Reg<u32, _MACPMTCSR>>

pub fn pd(&mut self) -> PD_W<'_>

Bit 0 - Power down

pub fn mpe(&mut self) -> MPE_W<'_>

Bit 1 - Magic Packet enable

pub fn wfe(&mut self) -> WFE_W<'_>

Bit 2 - Wakeup frame enable

pub fn mpr(&mut self) -> MPR_W<'_>

Bit 5 - Magic packet received

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 6 - Wakeup frame received

pub fn gu(&mut self) -> GU_W<'_>

Bit 9 - Global unicast

pub fn wffrpr(&mut self) -> WFFRPR_W<'_>

Bit 31 - Wakeup frame filter register pointer reset

impl W<u32, Reg<u32, _MACSR>>

pub fn pmts(&mut self) -> PMTS_W<'_>

Bit 3 - PMT status

pub fn mmcs(&mut self) -> MMCS_W<'_>

Bit 4 - MMC status

pub fn mmcrs(&mut self) -> MMCRS_W<'_>

Bit 5 - MMC receive status

pub fn mmcts(&mut self) -> MMCTS_W<'_>

Bit 6 - MMC transmit status

pub fn tsts(&mut self) -> TSTS_W<'_>

Bit 9 - Time stamp trigger status

impl W<u32, Reg<u32, _MACIMR>>

pub fn pmtim(&mut self) -> PMTIM_W<'_>

Bit 3 - PMT interrupt mask

pub fn tstim(&mut self) -> TSTIM_W<'_>

Bit 9 - Time stamp trigger interrupt mask

impl W<u32, Reg<u32, _MACA0HR>>

pub fn maca0h(&mut self) -> MACA0H_W<'_>

Bits 0:15 - MAC address0 high

impl W<u32, Reg<u32, _MACA0LR>>

pub fn maca0l(&mut self) -> MACA0L_W<'_>

Bits 0:31 - MAC address0 low

impl W<u32, Reg<u32, _MACA1HR>>

pub fn maca1h(&mut self) -> MACA1H_W<'_>

Bits 0:15 - MAC address1 high

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA1LR>>

pub fn maca1l(&mut self) -> MACA1L_W<'_>

Bits 0:31 - MAC address1 low

impl W<u32, Reg<u32, _MACA2HR>>

pub fn eth_maca2hr(&mut self) -> ETH_MACA2HR_W<'_>

Bits 0:15 - Ethernet MAC address 2 high register

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA2LR>>

pub fn maca2l(&mut self) -> MACA2L_W<'_>

Bits 0:30 - MAC address2 low

impl W<u32, Reg<u32, _MACA3HR>>

pub fn maca3h(&mut self) -> MACA3H_W<'_>

Bits 0:15 - MAC address3 high

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA3LR>>

pub fn mbca3l(&mut self) -> MBCA3L_W<'_>

Bits 0:31 - MAC address3 low

impl W<u32, Reg<u32, _PTPTSCR>>

pub fn tse(&mut self) -> TSE_W<'_>

Bit 0 - Time stamp enable

pub fn tsfcu(&mut self) -> TSFCU_W<'_>

Bit 1 - Time stamp fine or coarse update

pub fn tssti(&mut self) -> TSSTI_W<'_>

Bit 2 - Time stamp system time initialize

pub fn tsstu(&mut self) -> TSSTU_W<'_>

Bit 3 - Time stamp system time update

pub fn tsite(&mut self) -> TSITE_W<'_>

Bit 4 - Time stamp interrupt trigger enable

pub fn tsaru(&mut self) -> TSARU_W<'_>

Bit 5 - Time stamp addend register update

impl W<u32, Reg<u32, _PTPSSIR>>

pub fn stssi(&mut self) -> STSSI_W<'_>

Bits 0:7 - System time subsecond increment

impl W<u32, Reg<u32, _PTPTSHUR>>

pub fn tsus(&mut self) -> TSUS_W<'_>

Bits 0:31 - Time stamp update second

impl W<u32, Reg<u32, _PTPTSLUR>>

pub fn tsuss(&mut self) -> TSUSS_W<'_>

Bits 0:30 - Time stamp update subseconds

pub fn tsupns(&mut self) -> TSUPNS_W<'_>

Bit 31 - Time stamp update positive or negative sign

impl W<u32, Reg<u32, _PTPTSAR>>

pub fn tsa(&mut self) -> TSA_W<'_>

Bits 0:31 - Time stamp addend

impl W<u32, Reg<u32, _PTPTTHR>>

pub fn ttsh(&mut self) -> TTSH_W<'_>

Bits 0:31 - Target time stamp high

impl W<u32, Reg<u32, _PTPTTLR>>

pub fn ttsl(&mut self) -> TTSL_W<'_>

Bits 0:31 - Target time stamp low

impl W<u32, Reg<u32, _DMABMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 0 - Software reset

pub fn da(&mut self) -> DA_W<'_>

Bit 1 - DMA Arbitration

pub fn dsl(&mut self) -> DSL_W<'_>

Bits 2:6 - Descriptor skip length

pub fn pbl(&mut self) -> PBL_W<'_>

Bits 8:13 - Programmable burst length

pub fn rtpr(&mut self) -> RTPR_W<'_>

Bits 14:15 - Rx Tx priority ratio

pub fn fb(&mut self) -> FB_W<'_>

Bit 16 - Fixed burst

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 17:22 - Rx DMA PBL

pub fn usp(&mut self) -> USP_W<'_>

Bit 23 - Use separate PBL

pub fn fpm(&mut self) -> FPM_W<'_>

Bit 24 - 4xPBL mode

pub fn aab(&mut self) -> AAB_W<'_>

Bit 25 - Address-aligned beats

impl W<u32, Reg<u32, _DMATPDR>>

pub fn tpd(&mut self) -> TPD_W<'_>

Bits 0:31 - Transmit poll demand

impl W<u32, Reg<u32, _DMARPDR>>

pub fn rpd(&mut self) -> RPD_W<'_>

Bits 0:31 - Receive poll demand

impl W<u32, Reg<u32, _DMARDLAR>>

pub fn srl(&mut self) -> SRL_W<'_>

Bits 0:31 - Start of receive list

impl W<u32, Reg<u32, _DMATDLAR>>

pub fn stl(&mut self) -> STL_W<'_>

Bits 0:31 - Start of transmit list

impl W<u32, Reg<u32, _DMASR>>

pub fn ts(&mut self) -> TS_W<'_>

Bit 0 - Transmit status

pub fn tpss(&mut self) -> TPSS_W<'_>

Bit 1 - Transmit process stopped status

pub fn tbus(&mut self) -> TBUS_W<'_>

Bit 2 - Transmit buffer unavailable status

pub fn tjts(&mut self) -> TJTS_W<'_>

Bit 3 - Transmit jabber timeout status

pub fn ros(&mut self) -> ROS_W<'_>

Bit 4 - Receive overflow status

pub fn tus(&mut self) -> TUS_W<'_>

Bit 5 - Transmit underflow status

pub fn rs(&mut self) -> RS_W<'_>

Bit 6 - Receive status

pub fn rbus(&mut self) -> RBUS_W<'_>

Bit 7 - Receive buffer unavailable status

pub fn rpss(&mut self) -> RPSS_W<'_>

Bit 8 - Receive process stopped status

pub fn pwts(&mut self) -> PWTS_W<'_>

Bit 9 - Receive watchdog timeout status

pub fn ets(&mut self) -> ETS_W<'_>

Bit 10 - Early transmit status

pub fn fbes(&mut self) -> FBES_W<'_>

Bit 13 - Fatal bus error status

pub fn ers(&mut self) -> ERS_W<'_>

Bit 14 - Early receive status

pub fn ais(&mut self) -> AIS_W<'_>

Bit 15 - Abnormal interrupt summary

pub fn nis(&mut self) -> NIS_W<'_>

Bit 16 - Normal interrupt summary

impl W<u32, Reg<u32, _DMAOMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 1 - SR

pub fn osf(&mut self) -> OSF_W<'_>

Bit 2 - OSF

pub fn rtc(&mut self) -> RTC_W<'_>

Bits 3:4 - RTC

pub fn fugf(&mut self) -> FUGF_W<'_>

Bit 6 - FUGF

pub fn fef(&mut self) -> FEF_W<'_>

Bit 7 - FEF

pub fn st(&mut self) -> ST_W<'_>

Bit 13 - ST

pub fn ttc(&mut self) -> TTC_W<'_>

Bits 14:16 - TTC

pub fn ftf(&mut self) -> FTF_W<'_>

Bit 20 - FTF

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 21 - TSF

pub fn dfrf(&mut self) -> DFRF_W<'_>

Bit 24 - DFRF

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 25 - RSF

pub fn dtcefd(&mut self) -> DTCEFD_W<'_>

Bit 26 - DTCEFD

impl W<u32, Reg<u32, _DMAIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 0 - Transmit interrupt enable

pub fn tpsie(&mut self) -> TPSIE_W<'_>

Bit 1 - Transmit process stopped interrupt enable

pub fn tbuie(&mut self) -> TBUIE_W<'_>

Bit 2 - Transmit buffer unavailable interrupt enable

pub fn tjtie(&mut self) -> TJTIE_W<'_>

Bit 3 - Transmit jabber timeout interrupt enable

pub fn roie(&mut self) -> ROIE_W<'_>

Bit 4 - Overflow interrupt enable

pub fn tuie(&mut self) -> TUIE_W<'_>

Bit 5 - Underflow interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 6 - Receive interrupt enable

pub fn rbuie(&mut self) -> RBUIE_W<'_>

Bit 7 - Receive buffer unavailable interrupt enable

pub fn rpsie(&mut self) -> RPSIE_W<'_>

Bit 8 - Receive process stopped interrupt enable

pub fn rwtie(&mut self) -> RWTIE_W<'_>

Bit 9 - receive watchdog timeout interrupt enable

pub fn etie(&mut self) -> ETIE_W<'_>

Bit 10 - Early transmit interrupt enable

pub fn fbeie(&mut self) -> FBEIE_W<'_>

Bit 13 - Fatal bus error interrupt enable

pub fn erie(&mut self) -> ERIE_W<'_>

Bit 14 - Early receive interrupt enable

pub fn aise(&mut self) -> AISE_W<'_>

Bit 15 - Abnormal interrupt summary enable

pub fn nise(&mut self) -> NISE_W<'_>

Bit 16 - Normal interrupt summary enable

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn ep_id(&mut self) -> EP_ID_W<'_>

Bits 0:3 - Endpoint Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction of transaction

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

pub fn ctr(&mut self) -> CTR_W<'_>

Bit 15 - Correct transfer

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn dualmod(&mut self) -> DUALMOD_W<'_>

Bits 16:19 - Dual mode selection

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _SMPR2>>

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 15:18 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 15:18 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - CMDINDEX

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - WAITRESP

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - WAITINT

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - WAITPEND

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - CPSMEN

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SDIOSuspend

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - ENCMDcompl

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - nIEN

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE_ATACMD

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - DTDIR

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - DTMODE

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMAEN

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - DBLOCKSIZE

pub fn pwstart(&mut self) -> PWSTART_W<'_>

Bit 8 - PWSTART

pub fn pwstop(&mut self) -> PWSTOP_W<'_>

Bit 9 - PWSTOP

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - RWMOD

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SDIOEN

impl W<u32, Reg<u32, _ICR>>

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAILC

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAILC

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUTC

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUTC

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERRC

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERRC

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDRENDC

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENTC

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAENDC

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERRC

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKENDC

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOITC

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAENDC

impl W<u32, Reg<u32, _MASK>>

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - CCRCFAILIE

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - DCRCFAILIE

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - CTIMEOUTIE

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - DTIMEOUTIE

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - TXUNDERRIE

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - RXOVERRIE

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - CMDRENDIE

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - CMDSENTIE

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - DATAENDIE

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - STBITERRIE

pub fn dbackendie(&mut self) -> DBACKENDIE_W<'_>

Bit 10 - DBACKENDIE

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - CMDACTIE

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - TXACTIE

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - RXACTIE

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - TXFIFOHEIE

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - RXFIFOHFIE

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - TXFIFOFIE

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - RXFIFOFIE

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - TXFIFOEIE

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - RXFIFOEIE

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - TXDAVLIE

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - RXDAVLIE

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIOITIE

pub fn ceatendie(&mut self) -> CEATENDIE_W<'_>

Bit 23 - CEATENDIE

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - FIFOData

impl W<u32, Reg<u32, _ACTRL>>

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD_>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn dualmod(&mut self) -> DUALMOD_W<'_>

Bits 16:19 - Dual mode selection

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _SMPR2>>

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low Power Deep Sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power Down Deep Sleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear Wake-up Flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear STANDBY Flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power Voltage Detector Enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD Level Selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable Backup Domain write protection

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB High speed prescaler (APB2)

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 14:15 - ADC prescaler

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn afiorst(&mut self) -> AFIORST_W<'_>

Bit 0 - Alternate function I/O reset

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 2 - IO port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 3 - IO port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 4 - IO port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 5 - IO port D reset

pub fn adc1rst(&mut self) -> ADC1RST_W<'_>

Bit 9 - ADC 1 interface reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn bkprst(&mut self) -> BKPRST_W<'_>

Bit 27 - Backup interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 23 - USB reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - TIM4 timer reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn afioen(&mut self) -> AFIOEN_W<'_>

Bit 0 - Alternate function I/O clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 2 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 3 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 4 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 5 - I/O port D clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 9 - ADC 1 interface clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn bkpen(&mut self) -> BKPEN_W<'_>

Bit 27 - Backup interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 23 - USB clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - TIM4 Timer clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CRL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:1 - Port n.0 mode bits

pub fn cnf0(&mut self) -> CNF0_W<'_>

Bits 2:3 - Port n.0 configuration bits

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:5 - Port n.1 mode bits

pub fn cnf1(&mut self) -> CNF1_W<'_>

Bits 6:7 - Port n.1 configuration bits

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:9 - Port n.2 mode bits

pub fn cnf2(&mut self) -> CNF2_W<'_>

Bits 10:11 - Port n.2 configuration bits

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:13 - Port n.3 mode bits

pub fn cnf3(&mut self) -> CNF3_W<'_>

Bits 14:15 - Port n.3 configuration bits

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:17 - Port n.4 mode bits

pub fn cnf4(&mut self) -> CNF4_W<'_>

Bits 18:19 - Port n.4 configuration bits

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:21 - Port n.5 mode bits

pub fn cnf5(&mut self) -> CNF5_W<'_>

Bits 22:23 - Port n.5 configuration bits

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:25 - Port n.6 mode bits

pub fn cnf6(&mut self) -> CNF6_W<'_>

Bits 26:27 - Port n.6 configuration bits

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:29 - Port n.7 mode bits

pub fn cnf7(&mut self) -> CNF7_W<'_>

Bits 30:31 - Port n.7 configuration bits

impl W<u32, Reg<u32, _CRH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:1 - Port n.8 mode bits

pub fn cnf8(&mut self) -> CNF8_W<'_>

Bits 2:3 - Port n.8 configuration bits

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:5 - Port n.9 mode bits

pub fn cnf9(&mut self) -> CNF9_W<'_>

Bits 6:7 - Port n.9 configuration bits

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:9 - Port n.10 mode bits

pub fn cnf10(&mut self) -> CNF10_W<'_>

Bits 10:11 - Port n.10 configuration bits

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:13 - Port n.11 mode bits

pub fn cnf11(&mut self) -> CNF11_W<'_>

Bits 14:15 - Port n.11 configuration bits

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:17 - Port n.12 mode bits

pub fn cnf12(&mut self) -> CNF12_W<'_>

Bits 18:19 - Port n.12 configuration bits

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:21 - Port n.13 mode bits

pub fn cnf13(&mut self) -> CNF13_W<'_>

Bits 22:23 - Port n.13 configuration bits

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:25 - Port n.14 mode bits

pub fn cnf14(&mut self) -> CNF14_W<'_>

Bits 26:27 - Port n.14 configuration bits

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:29 - Port n.15 mode bits

pub fn cnf15(&mut self) -> CNF15_W<'_>

Bits 30:31 - Port n.15 configuration bits

impl W<u32, Reg<u32, _ODR>>

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data

impl W<u32, Reg<u32, _BSRR>>

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Set bit 0

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Set bit 1

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Set bit 1

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Set bit 3

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Set bit 4

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Set bit 5

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Set bit 6

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Set bit 7

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Set bit 8

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Set bit 9

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Set bit 10

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Set bit 11

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Set bit 12

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Set bit 13

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Set bit 14

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Set bit 15

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Reset bit 15

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Reset bit 1

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Reset bit 15

impl W<u32, Reg<u32, _LCKR>>

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port A Lock bit 0

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port A Lock bit 1

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port A Lock bit 2

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port A Lock bit 3

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port A Lock bit 4

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port A Lock bit 5

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port A Lock bit 6

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port A Lock bit 7

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port A Lock bit 8

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port A Lock bit 9

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port A Lock bit 10

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port A Lock bit 11

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port A Lock bit 12

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port A Lock bit 13

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port A Lock bit 14

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port A Lock bit 15

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lock key

impl W<u32, Reg<u32, _EVCR>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:3 - Pin selection

pub fn port(&mut self) -> PORT_W<'_>

Bits 4:6 - Port selection

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 7 - Event Output Enable

impl W<u32, Reg<u32, _MAPR>>

pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<'_>

Bit 0 - SPI1 remapping

pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<'_>

Bit 1 - I2C1 remapping

pub fn usart1_remap(&mut self) -> USART1_REMAP_W<'_>

Bit 2 - USART1 remapping

pub fn usart2_remap(&mut self) -> USART2_REMAP_W<'_>

Bit 3 - USART2 remapping

pub fn usart3_remap(&mut self) -> USART3_REMAP_W<'_>

Bits 4:5 - USART3 remapping

pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<'_>

Bits 6:7 - TIM1 remapping

pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<'_>

Bits 8:9 - TIM2 remapping

pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<'_>

Bits 10:11 - TIM3 remapping

pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<'_>

Bit 12 - TIM4 remapping

pub fn can_remap(&mut self) -> CAN_REMAP_W<'_>

Bits 13:14 - CAN1 remapping

pub fn pd01_remap(&mut self) -> PD01_REMAP_W<'_>

Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT

pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<'_>

Bit 16 - Set and cleared by software

pub fn adc1_etrginj_remap(&mut self) -> ADC1_ETRGINJ_REMAP_W<'_>

Bit 17 - ADC 1 External trigger injected conversion remapping

pub fn adc1_etrgreg_remap(&mut self) -> ADC1_ETRGREG_REMAP_W<'_>

Bit 18 - ADC 1 external trigger regular conversion remapping

pub fn adc2_etrginj_remap(&mut self) -> ADC2_ETRGINJ_REMAP_W<'_>

Bit 19 - ADC 2 external trigger injected conversion remapping

pub fn adc2_etrgreg_remap(&mut self) -> ADC2_ETRGREG_REMAP_W<'_>

Bit 20 - ADC 2 external trigger regular conversion remapping

pub fn swj_cfg(&mut self) -> SWJ_CFG_W<'_>

Bits 24:26 - Serial wire JTAG configuration

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI0 configuration

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI1 configuration

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI2 configuration

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI3 configuration

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI4 configuration

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI5 configuration

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI6 configuration

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI7 configuration

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI8 configuration

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI9 configuration

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10 configuration

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI11 configuration

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI12 configuration

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI13 configuration

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI14 configuration

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI15 configuration

impl W<u32, Reg<u32, _MAPR2>>

pub fn tim9_remap(&mut self) -> TIM9_REMAP_W<'_>

Bit 5 - TIM9 remapping

pub fn tim10_remap(&mut self) -> TIM10_REMAP_W<'_>

Bit 6 - TIM10 remapping

pub fn tim11_remap(&mut self) -> TIM11_REMAP_W<'_>

Bit 7 - TIM11 remapping

pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<'_>

Bit 8 - TIM13 remapping

pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<'_>

Bit 9 - TIM14 remapping

pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<'_>

Bit 10 - NADV connect/disconnect

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CRH>>

pub fn secie(&mut self) -> SECIE_W<'_>

Bit 0 - Second interrupt Enable

pub fn alrie(&mut self) -> ALRIE_W<'_>

Bit 1 - Alarm interrupt Enable

pub fn owie(&mut self) -> OWIE_W<'_>

Bit 2 - Overflow interrupt Enable

impl W<u32, Reg<u32, _CRL>>

pub fn secf(&mut self) -> SECF_W<'_>

Bit 0 - Second Flag

pub fn alrf(&mut self) -> ALRF_W<'_>

Bit 1 - Alarm Flag

pub fn owf(&mut self) -> OWF_W<'_>

Bit 2 - Overflow Flag

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 3 - Registers Synchronized Flag

pub fn cnf(&mut self) -> CNF_W<'_>

Bit 4 - Configuration Flag

impl W<u32, Reg<u32, _PRLH>>

pub fn prlh(&mut self) -> PRLH_W<'_>

Bits 0:3 - RTC Prescaler Load Register High

impl W<u32, Reg<u32, _PRLL>>

pub fn prll(&mut self) -> PRLL_W<'_>

Bits 0:15 - RTC Prescaler Divider Register Low

impl W<u32, Reg<u32, _CNTH>>

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 0:15 - RTC counter register high

impl W<u32, Reg<u32, _CNTL>>

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 0:15 - RTC counter register Low

impl W<u32, Reg<u32, _ALRH>>

pub fn alrh(&mut self) -> ALRH_W<'_>

Bits 0:15 - RTC alarm register high

impl W<u32, Reg<u32, _ALRL>>

pub fn alrl(&mut self) -> ALRL_W<'_>

Bits 0:15 - RTC alarm register low

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

impl W<u32, Reg<u32, _CFR>>

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early Wakeup Interrupt

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer Base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early Wakeup Interrupt

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn dualmod(&mut self) -> DUALMOD_W<'_>

Bits 16:19 - Dual mode selection

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _SMPR2>>

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Reset bit

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - Prefetch buffer enable

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash Address

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 8 - DBG_IWDG_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 9 - DBG_WWDG_STOP

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 11 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 12 - DBG_TIM3_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 15 - DBG_I2C1_SMBUS_TIMEOUT

impl W<u32, Reg<u32, _DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _BKP_DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _RTCCR>>

pub fn cal(&mut self) -> CAL_W<'_>

Bits 0:6 - Calibration value

pub fn cco(&mut self) -> CCO_W<'_>

Bit 7 - Calibration Clock Output

pub fn asoe(&mut self) -> ASOE_W<'_>

Bit 8 - Alarm or second output enable

pub fn asos(&mut self) -> ASOS_W<'_>

Bit 9 - Alarm or second output selection

impl W<u32, Reg<u32, _CR>>

pub fn tpe(&mut self) -> TPE_W<'_>

Bit 0 - Tamper pin enable

pub fn tpal(&mut self) -> TPAL_W<'_>

Bit 1 - Tamper pin active level

impl W<u32, Reg<u32, _CSR>>

pub fn cte(&mut self) -> CTE_W<'_>

Bit 0 - Clear Tamper event

pub fn cti(&mut self) -> CTI_W<'_>

Bit 1 - Clear Tamper Interrupt

pub fn tpie(&mut self) -> TPIE_W<'_>

Bit 2 - Tamper Pin interrupt enable

impl W<u32, Reg<u32, _BCR1>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _FS_DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _FS_DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _FS_DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _FS_DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _FS_DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _FS_DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _FS_GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _FS_GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _FS_GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _FS_GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _FS_GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _FS_GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _FS_GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _FS_GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_DEVICE>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _FS_CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _FS_HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _FS_HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _FS_HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _FS_HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 15:18 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 15:18 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel 1

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel 2

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel 3

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel 4

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA underrun interrupt enable

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn ep_id(&mut self) -> EP_ID_W<'_>

Bits 0:3 - Endpoint Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction of transaction

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

pub fn ctr(&mut self) -> CTR_W<'_>

Bit 15 - Correct transfer

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _SR>>

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - DR

impl W<u32, Reg<u32, _BRR>>

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - DIV_Fraction

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - DIV_Mantissa

impl W<u32, Reg<u32, _CR1>>

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _ACTRL>>

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD_>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel 1

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel 2

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel 3

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel 4

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _BCR1>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR2>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR2>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM2>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT2>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - Attribute memory x databus HiZ time

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - Attribute memory x hold time

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - Attribute memory x wait time

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - Attribute memory x setup time

impl W<u32, Reg<u32, _PCR3>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR3>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM3>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT3>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR4>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR4>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM4>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT4>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PIO4>>

pub fn iohizx(&mut self) -> IOHIZX_W<'_>

Bits 24:31 - IOHIZx

pub fn ioholdx(&mut self) -> IOHOLDX_W<'_>

Bits 16:23 - IOHOLDx

pub fn iowaitx(&mut self) -> IOWAITX_W<'_>

Bits 8:15 - IOWAITx

pub fn iosetx(&mut self) -> IOSETX_W<'_>

Bits 0:7 - IOSETx

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low Power Deep Sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power Down Deep Sleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear Wake-up Flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear STANDBY Flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power Voltage Detector Enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD Level Selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable Backup Domain write protection

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB High speed prescaler (APB2)

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 14:15 - ADC prescaler

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn usbpre(&mut self) -> USBPRE_W<'_>

Bit 22 - USB prescaler

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn afiorst(&mut self) -> AFIORST_W<'_>

Bit 0 - Alternate function I/O reset

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 2 - IO port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 3 - IO port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 4 - IO port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 5 - IO port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 6 - IO port E reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 7 - IO port F reset

pub fn iopgrst(&mut self) -> IOPGRST_W<'_>

Bit 8 - IO port G reset

pub fn adc1rst(&mut self) -> ADC1RST_W<'_>

Bit 9 - ADC 1 interface reset

pub fn adc2rst(&mut self) -> ADC2RST_W<'_>

Bit 10 - ADC 2 interface reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 13 - TIM8 timer reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn adc3rst(&mut self) -> ADC3RST_W<'_>

Bit 15 - ADC 3 interface reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>

Bit 19 - TIM9 timer reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>

Bit 20 - TIM10 timer reset

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>

Bit 21 - TIM11 timer reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - Timer 5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - Timer 12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - Timer 13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - Timer 14 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - UART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - UART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 23 - USB reset

pub fn canrst(&mut self) -> CANRST_W<'_>

Bit 25 - CAN reset

pub fn bkprst(&mut self) -> BKPRST_W<'_>

Bit 27 - Backup interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC interface reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn fsmcen(&mut self) -> FSMCEN_W<'_>

Bit 8 - FSMC clock enable

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 10 - SDIO clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn afioen(&mut self) -> AFIOEN_W<'_>

Bit 0 - Alternate function I/O clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 2 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 3 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 4 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 5 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 6 - I/O port E clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 7 - I/O port F clock enable

pub fn iopgen(&mut self) -> IOPGEN_W<'_>

Bit 8 - I/O port G clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 9 - ADC 1 interface clock enable

pub fn adc2en(&mut self) -> ADC2EN_W<'_>

Bit 10 - ADC 2 interface clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 Timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 13 - TIM8 Timer clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn adc3en(&mut self) -> ADC3EN_W<'_>

Bit 15 - ADC3 interface clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>

Bit 19 - TIM9 Timer clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>

Bit 20 - TIM10 Timer clock enable

pub fn tim11en(&mut self) -> TIM11EN_W<'_>

Bit 21 - TIM11 Timer clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - Timer 5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - Timer 12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - Timer 13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - Timer 14 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART 4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART 5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 23 - USB clock enable

pub fn canen(&mut self) -> CANEN_W<'_>

Bit 25 - CAN clock enable

pub fn bkpen(&mut self) -> BKPEN_W<'_>

Bit 27 - Backup interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC interface clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CRL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:1 - Port n.0 mode bits

pub fn cnf0(&mut self) -> CNF0_W<'_>

Bits 2:3 - Port n.0 configuration bits

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:5 - Port n.1 mode bits

pub fn cnf1(&mut self) -> CNF1_W<'_>

Bits 6:7 - Port n.1 configuration bits

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:9 - Port n.2 mode bits

pub fn cnf2(&mut self) -> CNF2_W<'_>

Bits 10:11 - Port n.2 configuration bits

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:13 - Port n.3 mode bits

pub fn cnf3(&mut self) -> CNF3_W<'_>

Bits 14:15 - Port n.3 configuration bits

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:17 - Port n.4 mode bits

pub fn cnf4(&mut self) -> CNF4_W<'_>

Bits 18:19 - Port n.4 configuration bits

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:21 - Port n.5 mode bits

pub fn cnf5(&mut self) -> CNF5_W<'_>

Bits 22:23 - Port n.5 configuration bits

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:25 - Port n.6 mode bits

pub fn cnf6(&mut self) -> CNF6_W<'_>

Bits 26:27 - Port n.6 configuration bits

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:29 - Port n.7 mode bits

pub fn cnf7(&mut self) -> CNF7_W<'_>

Bits 30:31 - Port n.7 configuration bits

impl W<u32, Reg<u32, _CRH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:1 - Port n.8 mode bits

pub fn cnf8(&mut self) -> CNF8_W<'_>

Bits 2:3 - Port n.8 configuration bits

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:5 - Port n.9 mode bits

pub fn cnf9(&mut self) -> CNF9_W<'_>

Bits 6:7 - Port n.9 configuration bits

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:9 - Port n.10 mode bits

pub fn cnf10(&mut self) -> CNF10_W<'_>

Bits 10:11 - Port n.10 configuration bits

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:13 - Port n.11 mode bits

pub fn cnf11(&mut self) -> CNF11_W<'_>

Bits 14:15 - Port n.11 configuration bits

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:17 - Port n.12 mode bits

pub fn cnf12(&mut self) -> CNF12_W<'_>

Bits 18:19 - Port n.12 configuration bits

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:21 - Port n.13 mode bits

pub fn cnf13(&mut self) -> CNF13_W<'_>

Bits 22:23 - Port n.13 configuration bits

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:25 - Port n.14 mode bits

pub fn cnf14(&mut self) -> CNF14_W<'_>

Bits 26:27 - Port n.14 configuration bits

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:29 - Port n.15 mode bits

pub fn cnf15(&mut self) -> CNF15_W<'_>

Bits 30:31 - Port n.15 configuration bits

impl W<u32, Reg<u32, _ODR>>

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data

impl W<u32, Reg<u32, _BSRR>>

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Set bit 0

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Set bit 1

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Set bit 1

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Set bit 3

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Set bit 4

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Set bit 5

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Set bit 6

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Set bit 7

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Set bit 8

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Set bit 9

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Set bit 10

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Set bit 11

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Set bit 12

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Set bit 13

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Set bit 14

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Set bit 15

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Reset bit 15

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Reset bit 1

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Reset bit 15

impl W<u32, Reg<u32, _LCKR>>

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port A Lock bit 0

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port A Lock bit 1

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port A Lock bit 2

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port A Lock bit 3

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port A Lock bit 4

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port A Lock bit 5

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port A Lock bit 6

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port A Lock bit 7

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port A Lock bit 8

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port A Lock bit 9

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port A Lock bit 10

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port A Lock bit 11

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port A Lock bit 12

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port A Lock bit 13

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port A Lock bit 14

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port A Lock bit 15

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lock key

impl W<u32, Reg<u32, _EVCR>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:3 - Pin selection

pub fn port(&mut self) -> PORT_W<'_>

Bits 4:6 - Port selection

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 7 - Event Output Enable

impl W<u32, Reg<u32, _MAPR>>

pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<'_>

Bit 0 - SPI1 remapping

pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<'_>

Bit 1 - I2C1 remapping

pub fn usart1_remap(&mut self) -> USART1_REMAP_W<'_>

Bit 2 - USART1 remapping

pub fn usart2_remap(&mut self) -> USART2_REMAP_W<'_>

Bit 3 - USART2 remapping

pub fn usart3_remap(&mut self) -> USART3_REMAP_W<'_>

Bits 4:5 - USART3 remapping

pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<'_>

Bits 6:7 - TIM1 remapping

pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<'_>

Bits 8:9 - TIM2 remapping

pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<'_>

Bits 10:11 - TIM3 remapping

pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<'_>

Bit 12 - TIM4 remapping

pub fn can_remap(&mut self) -> CAN_REMAP_W<'_>

Bits 13:14 - CAN1 remapping

pub fn pd01_remap(&mut self) -> PD01_REMAP_W<'_>

Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT

pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<'_>

Bit 16 - Set and cleared by software

pub fn adc1_etrginj_remap(&mut self) -> ADC1_ETRGINJ_REMAP_W<'_>

Bit 17 - ADC 1 External trigger injected conversion remapping

pub fn adc1_etrgreg_remap(&mut self) -> ADC1_ETRGREG_REMAP_W<'_>

Bit 18 - ADC 1 external trigger regular conversion remapping

pub fn adc2_etrginj_remap(&mut self) -> ADC2_ETRGINJ_REMAP_W<'_>

Bit 19 - ADC 2 external trigger injected conversion remapping

pub fn adc2_etrgreg_remap(&mut self) -> ADC2_ETRGREG_REMAP_W<'_>

Bit 20 - ADC 2 external trigger regular conversion remapping

pub fn swj_cfg(&mut self) -> SWJ_CFG_W<'_>

Bits 24:26 - Serial wire JTAG configuration

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI0 configuration

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI1 configuration

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI2 configuration

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI3 configuration

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI4 configuration

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI5 configuration

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI6 configuration

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI7 configuration

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI8 configuration

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI9 configuration

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10 configuration

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI11 configuration

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI12 configuration

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI13 configuration

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI14 configuration

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI15 configuration

impl W<u32, Reg<u32, _MAPR2>>

pub fn tim9_remap(&mut self) -> TIM9_REMAP_W<'_>

Bit 5 - TIM9 remapping

pub fn tim10_remap(&mut self) -> TIM10_REMAP_W<'_>

Bit 6 - TIM10 remapping

pub fn tim11_remap(&mut self) -> TIM11_REMAP_W<'_>

Bit 7 - TIM11 remapping

pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<'_>

Bit 8 - TIM13 remapping

pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<'_>

Bit 9 - TIM14 remapping

pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<'_>

Bit 10 - NADV connect/disconnect

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - CMDINDEX

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - WAITRESP

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - WAITINT

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - WAITPEND

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - CPSMEN

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SDIOSuspend

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - ENCMDcompl

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - nIEN

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE_ATACMD

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - DTDIR

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - DTMODE

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMAEN

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - DBLOCKSIZE

pub fn pwstart(&mut self) -> PWSTART_W<'_>

Bit 8 - PWSTART

pub fn pwstop(&mut self) -> PWSTOP_W<'_>

Bit 9 - PWSTOP

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - RWMOD

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SDIOEN

impl W<u32, Reg<u32, _ICR>>

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAILC

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAILC

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUTC

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUTC

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERRC

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERRC

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDRENDC

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENTC

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAENDC

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERRC

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKENDC

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOITC

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAENDC

impl W<u32, Reg<u32, _MASK>>

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - CCRCFAILIE

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - DCRCFAILIE

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - CTIMEOUTIE

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - DTIMEOUTIE

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - TXUNDERRIE

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - RXOVERRIE

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - CMDRENDIE

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - CMDSENTIE

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - DATAENDIE

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - STBITERRIE

pub fn dbackendie(&mut self) -> DBACKENDIE_W<'_>

Bit 10 - DBACKENDIE

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - CMDACTIE

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - TXACTIE

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - RXACTIE

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - TXFIFOHEIE

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - RXFIFOHFIE

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - TXFIFOFIE

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - RXFIFOFIE

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - TXFIFOEIE

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - RXFIFOEIE

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - TXDAVLIE

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - RXDAVLIE

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIOITIE

pub fn ceatendie(&mut self) -> CEATENDIE_W<'_>

Bit 23 - CEATENDIE

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - FIFOData

impl W<u32, Reg<u32, _CRH>>

pub fn secie(&mut self) -> SECIE_W<'_>

Bit 0 - Second interrupt Enable

pub fn alrie(&mut self) -> ALRIE_W<'_>

Bit 1 - Alarm interrupt Enable

pub fn owie(&mut self) -> OWIE_W<'_>

Bit 2 - Overflow interrupt Enable

impl W<u32, Reg<u32, _CRL>>

pub fn secf(&mut self) -> SECF_W<'_>

Bit 0 - Second Flag

pub fn alrf(&mut self) -> ALRF_W<'_>

Bit 1 - Alarm Flag

pub fn owf(&mut self) -> OWF_W<'_>

Bit 2 - Overflow Flag

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 3 - Registers Synchronized Flag

pub fn cnf(&mut self) -> CNF_W<'_>

Bit 4 - Configuration Flag

impl W<u32, Reg<u32, _PRLH>>

pub fn prlh(&mut self) -> PRLH_W<'_>

Bits 0:3 - RTC Prescaler Load Register High

impl W<u32, Reg<u32, _PRLL>>

pub fn prll(&mut self) -> PRLL_W<'_>

Bits 0:15 - RTC Prescaler Divider Register Low

impl W<u32, Reg<u32, _CNTH>>

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 0:15 - RTC counter register high

impl W<u32, Reg<u32, _CNTL>>

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 0:15 - RTC counter register Low

impl W<u32, Reg<u32, _ALRH>>

pub fn alrh(&mut self) -> ALRH_W<'_>

Bits 0:15 - RTC alarm register high

impl W<u32, Reg<u32, _ALRL>>

pub fn alrl(&mut self) -> ALRL_W<'_>

Bits 0:15 - RTC alarm register low

impl W<u32, Reg<u32, _DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _BKP_DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _RTCCR>>

pub fn cal(&mut self) -> CAL_W<'_>

Bits 0:6 - Calibration value

pub fn cco(&mut self) -> CCO_W<'_>

Bit 7 - Calibration Clock Output

pub fn asoe(&mut self) -> ASOE_W<'_>

Bit 8 - Alarm or second output enable

pub fn asos(&mut self) -> ASOS_W<'_>

Bit 9 - Alarm or second output selection

impl W<u32, Reg<u32, _CR>>

pub fn tpe(&mut self) -> TPE_W<'_>

Bit 0 - Tamper pin enable

pub fn tpal(&mut self) -> TPAL_W<'_>

Bit 1 - Tamper pin active level

impl W<u32, Reg<u32, _CSR>>

pub fn cte(&mut self) -> CTE_W<'_>

Bit 0 - Clear Tamper event

pub fn cti(&mut self) -> CTI_W<'_>

Bit 1 - Clear Tamper Interrupt

pub fn tpie(&mut self) -> TPIE_W<'_>

Bit 2 - Tamper Pin interrupt enable

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

impl W<u32, Reg<u32, _CFR>>

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early Wakeup Interrupt

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer Base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early Wakeup Interrupt

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn dualmod(&mut self) -> DUALMOD_W<'_>

Bits 16:19 - Dual mode selection

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 8 - DBG_IWDG_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 9 - DBG_WWDG_STOP

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 10 - DBG_TIM1_STOP

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 11 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 12 - DBG_TIM3_STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 13 - DBG_TIM4_STOP

pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<'_>

Bit 14 - DBG_CAN1_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 15 - DBG_I2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 16 - DBG_I2C2_SMBUS_TIMEOUT

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>

Bit 17 - DBG_TIM8_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 18 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 19 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 20 - DBG_TIM7_STOP

pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<'_>

Bit 21 - DBG_CAN2_STOP

impl W<u32, Reg<u32, _SR>>

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - DR

impl W<u32, Reg<u32, _BRR>>

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - DIV_Fraction

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - DIV_Mantissa

impl W<u32, Reg<u32, _CR1>>

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Reset bit

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - Prefetch buffer enable

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash Address

impl W<u32, Reg<u32, _EPR>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn ep_id(&mut self) -> EP_ID_W<'_>

Bits 0:3 - Endpoint Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction of transaction

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

pub fn ctr(&mut self) -> CTR_W<'_>

Bit 15 - Correct transfer

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _FS_DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _FS_DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _FS_DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _FS_DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _FS_DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _FS_DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _FS_GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _FS_GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _FS_GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _FS_GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _FS_GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _FS_GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _FS_GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _FS_GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_DEVICE>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _FS_CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _FS_HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _FS_HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _FS_HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _FS_HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _MMCCR>>

pub fn cr(&mut self) -> CR_W<'_>

Bit 0 - Counter reset

pub fn csr(&mut self) -> CSR_W<'_>

Bit 1 - Counter stop rollover

pub fn ror(&mut self) -> ROR_W<'_>

Bit 2 - Reset on read

pub fn mcf(&mut self) -> MCF_W<'_>

Bit 31 - MMC counter freeze

impl W<u32, Reg<u32, _MMCRIR>>

pub fn rfces(&mut self) -> RFCES_W<'_>

Bit 5 - Received frames CRC error status

pub fn rfaes(&mut self) -> RFAES_W<'_>

Bit 6 - Received frames alignment error status

pub fn rgufs(&mut self) -> RGUFS_W<'_>

Bit 17 - Received Good Unicast Frames Status

impl W<u32, Reg<u32, _MMCTIR>>

pub fn tgfscs(&mut self) -> TGFSCS_W<'_>

Bit 14 - Transmitted good frames single collision status

pub fn tgfmscs(&mut self) -> TGFMSCS_W<'_>

Bit 15 - Transmitted good frames more single collision status

pub fn tgfs(&mut self) -> TGFS_W<'_>

Bit 21 - Transmitted good frames status

impl W<u32, Reg<u32, _MMCRIMR>>

pub fn rfcem(&mut self) -> RFCEM_W<'_>

Bit 5 - Received frame CRC error mask

pub fn rfaem(&mut self) -> RFAEM_W<'_>

Bit 6 - Received frames alignment error mask

pub fn rgufm(&mut self) -> RGUFM_W<'_>

Bit 17 - Received good unicast frames mask

impl W<u32, Reg<u32, _MMCTIMR>>

pub fn tgfscm(&mut self) -> TGFSCM_W<'_>

Bit 14 - Transmitted good frames single collision mask

pub fn tgfmscm(&mut self) -> TGFMSCM_W<'_>

Bit 15 - Transmitted good frames more single collision mask

pub fn tgfm(&mut self) -> TGFM_W<'_>

Bit 21 - Transmitted good frames mask

impl W<u32, Reg<u32, _MACCR>>

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn dc(&mut self) -> DC_W<'_>

Bit 4 - Deferral check

pub fn bl(&mut self) -> BL_W<'_>

Bits 5:6 - Back-off limit

pub fn apcs(&mut self) -> APCS_W<'_>

Bit 7 - Automatic pad/CRC stripping

pub fn rd(&mut self) -> RD_W<'_>

Bit 9 - Retry disable

pub fn ipco(&mut self) -> IPCO_W<'_>

Bit 10 - IPv4 checksum offload

pub fn dm(&mut self) -> DM_W<'_>

Bit 11 - Duplex mode

pub fn lm(&mut self) -> LM_W<'_>

Bit 12 - Loopback mode

pub fn rod(&mut self) -> ROD_W<'_>

Bit 13 - Receive own disable

pub fn fes(&mut self) -> FES_W<'_>

Bit 14 - Fast Ethernet speed

pub fn csd(&mut self) -> CSD_W<'_>

Bit 16 - Carrier sense disable

pub fn ifg(&mut self) -> IFG_W<'_>

Bits 17:19 - Interframe gap

pub fn jd(&mut self) -> JD_W<'_>

Bit 22 - Jabber disable

pub fn wd(&mut self) -> WD_W<'_>

Bit 23 - Watchdog disable

impl W<u32, Reg<u32, _MACFFR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 0 - Promiscuous mode

pub fn hu(&mut self) -> HU_W<'_>

Bit 1 - Hash unicast

pub fn hm(&mut self) -> HM_W<'_>

Bit 2 - Hash multicast

pub fn daif(&mut self) -> DAIF_W<'_>

Bit 3 - Destination address inverse filtering

pub fn pam(&mut self) -> PAM_W<'_>

Bit 4 - Pass all multicast

pub fn bfd(&mut self) -> BFD_W<'_>

Bit 5 - Broadcast frames disable

pub fn pcf(&mut self) -> PCF_W<'_>

Bits 6:7 - Pass control frames

pub fn saif(&mut self) -> SAIF_W<'_>

Bit 8 - Source address inverse filtering

pub fn saf(&mut self) -> SAF_W<'_>

Bit 9 - Source address filter

pub fn hpf(&mut self) -> HPF_W<'_>

Bit 10 - Hash or perfect filter

pub fn ra(&mut self) -> RA_W<'_>

Bit 31 - Receive all

impl W<u32, Reg<u32, _MACHTHR>>

pub fn hth(&mut self) -> HTH_W<'_>

Bits 0:31 - Hash table high

impl W<u32, Reg<u32, _MACHTLR>>

pub fn htl(&mut self) -> HTL_W<'_>

Bits 0:31 - Hash table low

impl W<u32, Reg<u32, _MACMIIAR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - MII busy

pub fn mw(&mut self) -> MW_W<'_>

Bit 1 - MII write

pub fn cr(&mut self) -> CR_W<'_>

Bits 2:4 - Clock range

pub fn mr(&mut self) -> MR_W<'_>

Bits 6:10 - MII register

pub fn pa(&mut self) -> PA_W<'_>

Bits 11:15 - PHY address

impl W<u32, Reg<u32, _MACMIIDR>>

pub fn md(&mut self) -> MD_W<'_>

Bits 0:15 - MII data

impl W<u32, Reg<u32, _MACFCR>>

pub fn fcb_bpa(&mut self) -> FCB_BPA_W<'_>

Bit 0 - Flow control busy/back pressure activate

pub fn tfce(&mut self) -> TFCE_W<'_>

Bit 1 - Transmit flow control enable

pub fn rfce(&mut self) -> RFCE_W<'_>

Bit 2 - Receive flow control enable

pub fn upfd(&mut self) -> UPFD_W<'_>

Bit 3 - Unicast pause frame detect

pub fn plt(&mut self) -> PLT_W<'_>

Bits 4:5 - Pause low threshold

pub fn zqpd(&mut self) -> ZQPD_W<'_>

Bit 7 - Zero-quanta pause disable

pub fn pt(&mut self) -> PT_W<'_>

Bits 16:31 - Pass control frames

impl W<u32, Reg<u32, _MACVLANTR>>

pub fn vlanti(&mut self) -> VLANTI_W<'_>

Bits 0:15 - VLAN tag identifier (for receive frames)

pub fn vlantc(&mut self) -> VLANTC_W<'_>

Bit 16 - 12-bit VLAN tag comparison

impl W<u32, Reg<u32, _MACPMTCSR>>

pub fn pd(&mut self) -> PD_W<'_>

Bit 0 - Power down

pub fn mpe(&mut self) -> MPE_W<'_>

Bit 1 - Magic Packet enable

pub fn wfe(&mut self) -> WFE_W<'_>

Bit 2 - Wakeup frame enable

pub fn mpr(&mut self) -> MPR_W<'_>

Bit 5 - Magic packet received

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 6 - Wakeup frame received

pub fn gu(&mut self) -> GU_W<'_>

Bit 9 - Global unicast

pub fn wffrpr(&mut self) -> WFFRPR_W<'_>

Bit 31 - Wakeup frame filter register pointer reset

impl W<u32, Reg<u32, _MACSR>>

pub fn pmts(&mut self) -> PMTS_W<'_>

Bit 3 - PMT status

pub fn mmcs(&mut self) -> MMCS_W<'_>

Bit 4 - MMC status

pub fn mmcrs(&mut self) -> MMCRS_W<'_>

Bit 5 - MMC receive status

pub fn mmcts(&mut self) -> MMCTS_W<'_>

Bit 6 - MMC transmit status

pub fn tsts(&mut self) -> TSTS_W<'_>

Bit 9 - Time stamp trigger status

impl W<u32, Reg<u32, _MACIMR>>

pub fn pmtim(&mut self) -> PMTIM_W<'_>

Bit 3 - PMT interrupt mask

pub fn tstim(&mut self) -> TSTIM_W<'_>

Bit 9 - Time stamp trigger interrupt mask

impl W<u32, Reg<u32, _MACA0HR>>

pub fn maca0h(&mut self) -> MACA0H_W<'_>

Bits 0:15 - MAC address0 high

impl W<u32, Reg<u32, _MACA0LR>>

pub fn maca0l(&mut self) -> MACA0L_W<'_>

Bits 0:31 - MAC address0 low

impl W<u32, Reg<u32, _MACA1HR>>

pub fn maca1h(&mut self) -> MACA1H_W<'_>

Bits 0:15 - MAC address1 high

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA1LR>>

pub fn maca1l(&mut self) -> MACA1L_W<'_>

Bits 0:31 - MAC address1 low

impl W<u32, Reg<u32, _MACA2HR>>

pub fn eth_maca2hr(&mut self) -> ETH_MACA2HR_W<'_>

Bits 0:15 - Ethernet MAC address 2 high register

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA2LR>>

pub fn maca2l(&mut self) -> MACA2L_W<'_>

Bits 0:30 - MAC address2 low

impl W<u32, Reg<u32, _MACA3HR>>

pub fn maca3h(&mut self) -> MACA3H_W<'_>

Bits 0:15 - MAC address3 high

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA3LR>>

pub fn mbca3l(&mut self) -> MBCA3L_W<'_>

Bits 0:31 - MAC address3 low

impl W<u32, Reg<u32, _PTPTSCR>>

pub fn tse(&mut self) -> TSE_W<'_>

Bit 0 - Time stamp enable

pub fn tsfcu(&mut self) -> TSFCU_W<'_>

Bit 1 - Time stamp fine or coarse update

pub fn tssti(&mut self) -> TSSTI_W<'_>

Bit 2 - Time stamp system time initialize

pub fn tsstu(&mut self) -> TSSTU_W<'_>

Bit 3 - Time stamp system time update

pub fn tsite(&mut self) -> TSITE_W<'_>

Bit 4 - Time stamp interrupt trigger enable

pub fn tsaru(&mut self) -> TSARU_W<'_>

Bit 5 - Time stamp addend register update

impl W<u32, Reg<u32, _PTPSSIR>>

pub fn stssi(&mut self) -> STSSI_W<'_>

Bits 0:7 - System time subsecond increment

impl W<u32, Reg<u32, _PTPTSHUR>>

pub fn tsus(&mut self) -> TSUS_W<'_>

Bits 0:31 - Time stamp update second

impl W<u32, Reg<u32, _PTPTSLUR>>

pub fn tsuss(&mut self) -> TSUSS_W<'_>

Bits 0:30 - Time stamp update subseconds

pub fn tsupns(&mut self) -> TSUPNS_W<'_>

Bit 31 - Time stamp update positive or negative sign

impl W<u32, Reg<u32, _PTPTSAR>>

pub fn tsa(&mut self) -> TSA_W<'_>

Bits 0:31 - Time stamp addend

impl W<u32, Reg<u32, _PTPTTHR>>

pub fn ttsh(&mut self) -> TTSH_W<'_>

Bits 0:31 - Target time stamp high

impl W<u32, Reg<u32, _PTPTTLR>>

pub fn ttsl(&mut self) -> TTSL_W<'_>

Bits 0:31 - Target time stamp low

impl W<u32, Reg<u32, _DMABMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 0 - Software reset

pub fn da(&mut self) -> DA_W<'_>

Bit 1 - DMA Arbitration

pub fn dsl(&mut self) -> DSL_W<'_>

Bits 2:6 - Descriptor skip length

pub fn pbl(&mut self) -> PBL_W<'_>

Bits 8:13 - Programmable burst length

pub fn rtpr(&mut self) -> RTPR_W<'_>

Bits 14:15 - Rx Tx priority ratio

pub fn fb(&mut self) -> FB_W<'_>

Bit 16 - Fixed burst

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 17:22 - Rx DMA PBL

pub fn usp(&mut self) -> USP_W<'_>

Bit 23 - Use separate PBL

pub fn fpm(&mut self) -> FPM_W<'_>

Bit 24 - 4xPBL mode

pub fn aab(&mut self) -> AAB_W<'_>

Bit 25 - Address-aligned beats

impl W<u32, Reg<u32, _DMATPDR>>

pub fn tpd(&mut self) -> TPD_W<'_>

Bits 0:31 - Transmit poll demand

impl W<u32, Reg<u32, _DMARPDR>>

pub fn rpd(&mut self) -> RPD_W<'_>

Bits 0:31 - Receive poll demand

impl W<u32, Reg<u32, _DMARDLAR>>

pub fn srl(&mut self) -> SRL_W<'_>

Bits 0:31 - Start of receive list

impl W<u32, Reg<u32, _DMATDLAR>>

pub fn stl(&mut self) -> STL_W<'_>

Bits 0:31 - Start of transmit list

impl W<u32, Reg<u32, _DMASR>>

pub fn ts(&mut self) -> TS_W<'_>

Bit 0 - Transmit status

pub fn tpss(&mut self) -> TPSS_W<'_>

Bit 1 - Transmit process stopped status

pub fn tbus(&mut self) -> TBUS_W<'_>

Bit 2 - Transmit buffer unavailable status

pub fn tjts(&mut self) -> TJTS_W<'_>

Bit 3 - Transmit jabber timeout status

pub fn ros(&mut self) -> ROS_W<'_>

Bit 4 - Receive overflow status

pub fn tus(&mut self) -> TUS_W<'_>

Bit 5 - Transmit underflow status

pub fn rs(&mut self) -> RS_W<'_>

Bit 6 - Receive status

pub fn rbus(&mut self) -> RBUS_W<'_>

Bit 7 - Receive buffer unavailable status

pub fn rpss(&mut self) -> RPSS_W<'_>

Bit 8 - Receive process stopped status

pub fn pwts(&mut self) -> PWTS_W<'_>

Bit 9 - Receive watchdog timeout status

pub fn ets(&mut self) -> ETS_W<'_>

Bit 10 - Early transmit status

pub fn fbes(&mut self) -> FBES_W<'_>

Bit 13 - Fatal bus error status

pub fn ers(&mut self) -> ERS_W<'_>

Bit 14 - Early receive status

pub fn ais(&mut self) -> AIS_W<'_>

Bit 15 - Abnormal interrupt summary

pub fn nis(&mut self) -> NIS_W<'_>

Bit 16 - Normal interrupt summary

impl W<u32, Reg<u32, _DMAOMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 1 - SR

pub fn osf(&mut self) -> OSF_W<'_>

Bit 2 - OSF

pub fn rtc(&mut self) -> RTC_W<'_>

Bits 3:4 - RTC

pub fn fugf(&mut self) -> FUGF_W<'_>

Bit 6 - FUGF

pub fn fef(&mut self) -> FEF_W<'_>

Bit 7 - FEF

pub fn st(&mut self) -> ST_W<'_>

Bit 13 - ST

pub fn ttc(&mut self) -> TTC_W<'_>

Bits 14:16 - TTC

pub fn ftf(&mut self) -> FTF_W<'_>

Bit 20 - FTF

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 21 - TSF

pub fn dfrf(&mut self) -> DFRF_W<'_>

Bit 24 - DFRF

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 25 - RSF

pub fn dtcefd(&mut self) -> DTCEFD_W<'_>

Bit 26 - DTCEFD

impl W<u32, Reg<u32, _DMAIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 0 - Transmit interrupt enable

pub fn tpsie(&mut self) -> TPSIE_W<'_>

Bit 1 - Transmit process stopped interrupt enable

pub fn tbuie(&mut self) -> TBUIE_W<'_>

Bit 2 - Transmit buffer unavailable interrupt enable

pub fn tjtie(&mut self) -> TJTIE_W<'_>

Bit 3 - Transmit jabber timeout interrupt enable

pub fn roie(&mut self) -> ROIE_W<'_>

Bit 4 - Overflow interrupt enable

pub fn tuie(&mut self) -> TUIE_W<'_>

Bit 5 - Underflow interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 6 - Receive interrupt enable

pub fn rbuie(&mut self) -> RBUIE_W<'_>

Bit 7 - Receive buffer unavailable interrupt enable

pub fn rpsie(&mut self) -> RPSIE_W<'_>

Bit 8 - Receive process stopped interrupt enable

pub fn rwtie(&mut self) -> RWTIE_W<'_>

Bit 9 - receive watchdog timeout interrupt enable

pub fn etie(&mut self) -> ETIE_W<'_>

Bit 10 - Early transmit interrupt enable

pub fn fbeie(&mut self) -> FBEIE_W<'_>

Bit 13 - Fatal bus error interrupt enable

pub fn erie(&mut self) -> ERIE_W<'_>

Bit 14 - Early receive interrupt enable

pub fn aise(&mut self) -> AISE_W<'_>

Bit 15 - Abnormal interrupt summary enable

pub fn nise(&mut self) -> NISE_W<'_>

Bit 16 - Normal interrupt summary enable

impl W<u32, Reg<u32, _ACTRL>>

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD_>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sample time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sample time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sample time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sample time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sample time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sample time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sample time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sample time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sample time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sample time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sample time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sample time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sample time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sample time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sample time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sample time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sample time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sample time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low Power Deep Sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power Down Deep Sleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear Wake-up Flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear STANDBY Flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power Voltage Detector Enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD Level Selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable Backup Domain write protection

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pll2on(&mut self) -> PLL2ON_W<'_>

Bit 26 - PLL2 enable

pub fn pll3on(&mut self) -> PLL3ON_W<'_>

Bit 28 - PLL3 enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB High speed prescaler (APB2)

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 14:15 - ADC prescaler

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn otgfspre(&mut self) -> OTGFSPRE_W<'_>

Bit 22 - USB OTG FS prescaler

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:27 - Microcontroller clock output

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn pll2rdyie(&mut self) -> PLL2RDYIE_W<'_>

Bit 13 - PLL2 Ready Interrupt Enable

pub fn pll3rdyie(&mut self) -> PLL3RDYIE_W<'_>

Bit 14 - PLL3 Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn pll2rdyc(&mut self) -> PLL2RDYC_W<'_>

Bit 21 - PLL2 Ready Interrupt Clear

pub fn pll3rdyc(&mut self) -> PLL3RDYC_W<'_>

Bit 22 - PLL3 Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn afiorst(&mut self) -> AFIORST_W<'_>

Bit 0 - Alternate function I/O reset

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 2 - IO port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 3 - IO port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 4 - IO port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 5 - IO port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 6 - IO port E reset

pub fn adc1rst(&mut self) -> ADC1RST_W<'_>

Bit 9 - ADC 1 interface reset

pub fn adc2rst(&mut self) -> ADC2RST_W<'_>

Bit 10 - ADC 2 interface reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - Timer 5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - USART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - USART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>

Bit 25 - CAN1 reset

pub fn can2rst(&mut self) -> CAN2RST_W<'_>

Bit 26 - CAN2 reset

pub fn bkprst(&mut self) -> BKPRST_W<'_>

Bit 27 - Backup interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC interface reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>

Bit 12 - USB OTG FS clock enable

pub fn ethmacen(&mut self) -> ETHMACEN_W<'_>

Bit 14 - Ethernet MAC clock enable

pub fn ethmactxen(&mut self) -> ETHMACTXEN_W<'_>

Bit 15 - Ethernet MAC TX clock enable

pub fn ethmacrxen(&mut self) -> ETHMACRXEN_W<'_>

Bit 16 - Ethernet MAC RX clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn afioen(&mut self) -> AFIOEN_W<'_>

Bit 0 - Alternate function I/O clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 2 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 3 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 4 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 5 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 6 - I/O port E clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 9 - ADC 1 interface clock enable

pub fn adc2en(&mut self) -> ADC2EN_W<'_>

Bit 10 - ADC 2 interface clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 Timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - Timer 5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART 4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART 5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>

Bit 25 - CAN1 clock enable

pub fn can2en(&mut self) -> CAN2EN_W<'_>

Bit 26 - CAN2 clock enable

pub fn bkpen(&mut self) -> BKPEN_W<'_>

Bit 27 - Backup interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC interface clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>

Bit 12 - USB OTG FS reset

pub fn ethmacrst(&mut self) -> ETHMACRST_W<'_>

Bit 14 - Ethernet MAC reset

impl W<u32, Reg<u32, _CFGR2>>

pub fn prediv1(&mut self) -> PREDIV1_W<'_>

Bits 0:3 - PREDIV1 division factor

pub fn prediv2(&mut self) -> PREDIV2_W<'_>

Bits 4:7 - PREDIV2 division factor

pub fn pll2mul(&mut self) -> PLL2MUL_W<'_>

Bits 8:11 - PLL2 Multiplication Factor

pub fn pll3mul(&mut self) -> PLL3MUL_W<'_>

Bits 12:15 - PLL3 Multiplication Factor

pub fn prediv1src(&mut self) -> PREDIV1SRC_W<'_>

Bit 16 - PREDIV1 entry clock source

pub fn i2s2src(&mut self) -> I2S2SRC_W<'_>

Bit 17 - I2S2 clock source

pub fn i2s3src(&mut self) -> I2S3SRC_W<'_>

Bit 18 - I2S3 clock source

impl W<u32, Reg<u32, _CRL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:1 - Port n.0 mode bits

pub fn cnf0(&mut self) -> CNF0_W<'_>

Bits 2:3 - Port n.0 configuration bits

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:5 - Port n.1 mode bits

pub fn cnf1(&mut self) -> CNF1_W<'_>

Bits 6:7 - Port n.1 configuration bits

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:9 - Port n.2 mode bits

pub fn cnf2(&mut self) -> CNF2_W<'_>

Bits 10:11 - Port n.2 configuration bits

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:13 - Port n.3 mode bits

pub fn cnf3(&mut self) -> CNF3_W<'_>

Bits 14:15 - Port n.3 configuration bits

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:17 - Port n.4 mode bits

pub fn cnf4(&mut self) -> CNF4_W<'_>

Bits 18:19 - Port n.4 configuration bits

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:21 - Port n.5 mode bits

pub fn cnf5(&mut self) -> CNF5_W<'_>

Bits 22:23 - Port n.5 configuration bits

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:25 - Port n.6 mode bits

pub fn cnf6(&mut self) -> CNF6_W<'_>

Bits 26:27 - Port n.6 configuration bits

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:29 - Port n.7 mode bits

pub fn cnf7(&mut self) -> CNF7_W<'_>

Bits 30:31 - Port n.7 configuration bits

impl W<u32, Reg<u32, _CRH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:1 - Port n.8 mode bits

pub fn cnf8(&mut self) -> CNF8_W<'_>

Bits 2:3 - Port n.8 configuration bits

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:5 - Port n.9 mode bits

pub fn cnf9(&mut self) -> CNF9_W<'_>

Bits 6:7 - Port n.9 configuration bits

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:9 - Port n.10 mode bits

pub fn cnf10(&mut self) -> CNF10_W<'_>

Bits 10:11 - Port n.10 configuration bits

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:13 - Port n.11 mode bits

pub fn cnf11(&mut self) -> CNF11_W<'_>

Bits 14:15 - Port n.11 configuration bits

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:17 - Port n.12 mode bits

pub fn cnf12(&mut self) -> CNF12_W<'_>

Bits 18:19 - Port n.12 configuration bits

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:21 - Port n.13 mode bits

pub fn cnf13(&mut self) -> CNF13_W<'_>

Bits 22:23 - Port n.13 configuration bits

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:25 - Port n.14 mode bits

pub fn cnf14(&mut self) -> CNF14_W<'_>

Bits 26:27 - Port n.14 configuration bits

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:29 - Port n.15 mode bits

pub fn cnf15(&mut self) -> CNF15_W<'_>

Bits 30:31 - Port n.15 configuration bits

impl W<u32, Reg<u32, _ODR>>

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data

impl W<u32, Reg<u32, _BSRR>>

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Set bit 0

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Set bit 1

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Set bit 1

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Set bit 3

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Set bit 4

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Set bit 5

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Set bit 6

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Set bit 7

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Set bit 8

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Set bit 9

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Set bit 10

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Set bit 11

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Set bit 12

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Set bit 13

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Set bit 14

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Set bit 15

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Reset bit 15

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Reset bit 1

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Reset bit 15

impl W<u32, Reg<u32, _LCKR>>

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port A Lock bit 0

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port A Lock bit 1

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port A Lock bit 2

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port A Lock bit 3

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port A Lock bit 4

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port A Lock bit 5

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port A Lock bit 6

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port A Lock bit 7

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port A Lock bit 8

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port A Lock bit 9

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port A Lock bit 10

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port A Lock bit 11

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port A Lock bit 12

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port A Lock bit 13

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port A Lock bit 14

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port A Lock bit 15

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lock key

impl W<u32, Reg<u32, _EVCR>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:3 - Pin selection

pub fn port(&mut self) -> PORT_W<'_>

Bits 4:6 - Port selection

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 7 - Event Output Enable

impl W<u32, Reg<u32, _MAPR>>

pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<'_>

Bit 0 - SPI1 remapping

pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<'_>

Bit 1 - I2C1 remapping

pub fn usart1_remap(&mut self) -> USART1_REMAP_W<'_>

Bit 2 - USART1 remapping

pub fn usart2_remap(&mut self) -> USART2_REMAP_W<'_>

Bit 3 - USART2 remapping

pub fn usart3_remap(&mut self) -> USART3_REMAP_W<'_>

Bits 4:5 - USART3 remapping

pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<'_>

Bits 6:7 - TIM1 remapping

pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<'_>

Bits 8:9 - TIM2 remapping

pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<'_>

Bits 10:11 - TIM3 remapping

pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<'_>

Bit 12 - TIM4 remapping

pub fn can1_remap(&mut self) -> CAN1_REMAP_W<'_>

Bits 13:14 - CAN1 remapping

pub fn pd01_remap(&mut self) -> PD01_REMAP_W<'_>

Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT

pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<'_>

Bit 16 - Set and cleared by software

pub fn eth_remap(&mut self) -> ETH_REMAP_W<'_>

Bit 21 - Ethernet MAC I/O remapping

pub fn can2_remap(&mut self) -> CAN2_REMAP_W<'_>

Bit 22 - CAN2 I/O remapping

pub fn mii_rmii_sel(&mut self) -> MII_RMII_SEL_W<'_>

Bit 23 - MII or RMII selection

pub fn swj_cfg(&mut self) -> SWJ_CFG_W<'_>

Bits 24:26 - Serial wire JTAG configuration

pub fn spi3_remap(&mut self) -> SPI3_REMAP_W<'_>

Bit 28 - SPI3/I2S3 remapping

pub fn tim2itr1_iremap(&mut self) -> TIM2ITR1_IREMAP_W<'_>

Bit 29 - TIM2 internal trigger 1 remapping

pub fn ptp_pps_remap(&mut self) -> PTP_PPS_REMAP_W<'_>

Bit 30 - Ethernet PTP PPS remapping

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI0 configuration

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI1 configuration

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI2 configuration

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI3 configuration

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI4 configuration

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI5 configuration

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI6 configuration

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI7 configuration

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI8 configuration

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI9 configuration

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10 configuration

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI11 configuration

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI12 configuration

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI13 configuration

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI14 configuration

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI15 configuration

impl W<u32, Reg<u32, _MAPR2>>

pub fn tim9_remap(&mut self) -> TIM9_REMAP_W<'_>

Bit 5 - TIM9 remapping

pub fn tim10_remap(&mut self) -> TIM10_REMAP_W<'_>

Bit 6 - TIM10 remapping

pub fn tim11_remap(&mut self) -> TIM11_REMAP_W<'_>

Bit 7 - TIM11 remapping

pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<'_>

Bit 8 - TIM13 remapping

pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<'_>

Bit 9 - TIM14 remapping

pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<'_>

Bit 10 - NADV connect/disconnect

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CRH>>

pub fn secie(&mut self) -> SECIE_W<'_>

Bit 0 - Second interrupt Enable

pub fn alrie(&mut self) -> ALRIE_W<'_>

Bit 1 - Alarm interrupt Enable

pub fn owie(&mut self) -> OWIE_W<'_>

Bit 2 - Overflow interrupt Enable

impl W<u32, Reg<u32, _CRL>>

pub fn secf(&mut self) -> SECF_W<'_>

Bit 0 - Second Flag

pub fn alrf(&mut self) -> ALRF_W<'_>

Bit 1 - Alarm Flag

pub fn owf(&mut self) -> OWF_W<'_>

Bit 2 - Overflow Flag

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 3 - Registers Synchronized Flag

pub fn cnf(&mut self) -> CNF_W<'_>

Bit 4 - Configuration Flag

impl W<u32, Reg<u32, _PRLH>>

pub fn prlh(&mut self) -> PRLH_W<'_>

Bits 0:3 - RTC Prescaler Load Register High

impl W<u32, Reg<u32, _PRLL>>

pub fn prll(&mut self) -> PRLL_W<'_>

Bits 0:15 - RTC Prescaler Divider Register Low

impl W<u32, Reg<u32, _CNTH>>

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 0:15 - RTC counter register high

impl W<u32, Reg<u32, _CNTL>>

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 0:15 - RTC counter register Low

impl W<u32, Reg<u32, _ALRH>>

pub fn alrh(&mut self) -> ALRH_W<'_>

Bits 0:15 - RTC alarm register high

impl W<u32, Reg<u32, _ALRL>>

pub fn alrl(&mut self) -> ALRL_W<'_>

Bits 0:15 - RTC alarm register low

impl W<u32, Reg<u32, _DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _BKP_DR>>

pub fn d(&mut self) -> D_W<'_>

Bits 0:15 - Backup data

impl W<u32, Reg<u32, _RTCCR>>

pub fn cal(&mut self) -> CAL_W<'_>

Bits 0:6 - Calibration value

pub fn cco(&mut self) -> CCO_W<'_>

Bit 7 - Calibration Clock Output

pub fn asoe(&mut self) -> ASOE_W<'_>

Bit 8 - Alarm or second output enable

pub fn asos(&mut self) -> ASOS_W<'_>

Bit 9 - Alarm or second output selection

impl W<u32, Reg<u32, _CR>>

pub fn tpe(&mut self) -> TPE_W<'_>

Bit 0 - Tamper pin enable

pub fn tpal(&mut self) -> TPAL_W<'_>

Bit 1 - Tamper pin active level

impl W<u32, Reg<u32, _CSR>>

pub fn cte(&mut self) -> CTE_W<'_>

Bit 0 - Clear Tamper event

pub fn cti(&mut self) -> CTI_W<'_>

Bit 1 - Clear Tamper Interrupt

pub fn tpie(&mut self) -> TPIE_W<'_>

Bit 2 - Tamper Pin interrupt enable

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

impl W<u32, Reg<u32, _CFR>>

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early Wakeup Interrupt

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer Base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early Wakeup Interrupt

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn dualmod(&mut self) -> DUALMOD_W<'_>

Bits 16:19 - Dual mode selection

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _MACCR>>

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn dc(&mut self) -> DC_W<'_>

Bit 4 - Deferral check

pub fn bl(&mut self) -> BL_W<'_>

Bits 5:6 - Back-off limit

pub fn apcs(&mut self) -> APCS_W<'_>

Bit 7 - Automatic pad/CRC stripping

pub fn rd(&mut self) -> RD_W<'_>

Bit 9 - Retry disable

pub fn ipco(&mut self) -> IPCO_W<'_>

Bit 10 - IPv4 checksum offload

pub fn dm(&mut self) -> DM_W<'_>

Bit 11 - Duplex mode

pub fn lm(&mut self) -> LM_W<'_>

Bit 12 - Loopback mode

pub fn rod(&mut self) -> ROD_W<'_>

Bit 13 - Receive own disable

pub fn fes(&mut self) -> FES_W<'_>

Bit 14 - Fast Ethernet speed

pub fn csd(&mut self) -> CSD_W<'_>

Bit 16 - Carrier sense disable

pub fn ifg(&mut self) -> IFG_W<'_>

Bits 17:19 - Interframe gap

pub fn jd(&mut self) -> JD_W<'_>

Bit 22 - Jabber disable

pub fn wd(&mut self) -> WD_W<'_>

Bit 23 - Watchdog disable

impl W<u32, Reg<u32, _MACFFR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 0 - Promiscuous mode

pub fn hu(&mut self) -> HU_W<'_>

Bit 1 - Hash unicast

pub fn hm(&mut self) -> HM_W<'_>

Bit 2 - Hash multicast

pub fn daif(&mut self) -> DAIF_W<'_>

Bit 3 - Destination address unique filtering

pub fn pam(&mut self) -> PAM_W<'_>

Bit 4 - Pass all multicast

pub fn bfd(&mut self) -> BFD_W<'_>

Bit 5 - Broadcast frames disable

pub fn pcf(&mut self) -> PCF_W<'_>

Bits 6:7 - Pass control frames

pub fn saif(&mut self) -> SAIF_W<'_>

Bit 8 - Source address inverse filtering

pub fn saf(&mut self) -> SAF_W<'_>

Bit 9 - Source address filter

pub fn hpf(&mut self) -> HPF_W<'_>

Bit 10 - Hash or perfect filter

pub fn ra(&mut self) -> RA_W<'_>

Bit 31 - Receive all

impl W<u32, Reg<u32, _MACHTHR>>

pub fn hth(&mut self) -> HTH_W<'_>

Bits 0:31 - Upper 32 bits of hash table

impl W<u32, Reg<u32, _MACHTLR>>

pub fn htl(&mut self) -> HTL_W<'_>

Bits 0:31 - Lower 32 bits of hash table

impl W<u32, Reg<u32, _MACMIIAR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - MII busy

pub fn mw(&mut self) -> MW_W<'_>

Bit 1 - MII write

pub fn cr(&mut self) -> CR_W<'_>

Bits 2:4 - Clock range

pub fn mr(&mut self) -> MR_W<'_>

Bits 6:10 - MII register - select the desired MII register in the PHY device

pub fn pa(&mut self) -> PA_W<'_>

Bits 11:15 - PHY address - select which of possible 32 PHYs is being accessed

impl W<u32, Reg<u32, _MACMIIDR>>

pub fn md(&mut self) -> MD_W<'_>

Bits 0:15 - MII data read from/written to the PHY

impl W<u32, Reg<u32, _MACFCR>>

pub fn fcb(&mut self) -> FCB_W<'_>

Bit 0 - Flow control busy/back pressure activate

pub fn tfce(&mut self) -> TFCE_W<'_>

Bit 1 - Transmit flow control enable

pub fn rfce(&mut self) -> RFCE_W<'_>

Bit 2 - Receive flow control enable

pub fn upfd(&mut self) -> UPFD_W<'_>

Bit 3 - Unicast pause frame detect

pub fn plt(&mut self) -> PLT_W<'_>

Bits 4:5 - Pause low threshold

pub fn zqpd(&mut self) -> ZQPD_W<'_>

Bit 7 - Zero-quanta pause disable

pub fn pt(&mut self) -> PT_W<'_>

Bits 16:31 - Pause time

impl W<u32, Reg<u32, _MACVLANTR>>

pub fn vlanti(&mut self) -> VLANTI_W<'_>

Bits 0:15 - VLAN tag identifier (for receive frames)

pub fn vlantc(&mut self) -> VLANTC_W<'_>

Bit 16 - 12-bit VLAN tag comparison

impl W<u32, Reg<u32, _MACPMTCSR>>

pub fn pd(&mut self) -> PD_W<'_>

Bit 0 - Power down

pub fn mpe(&mut self) -> MPE_W<'_>

Bit 1 - Magic packet enable

pub fn wfe(&mut self) -> WFE_W<'_>

Bit 2 - Wakeup frame enable

pub fn mpr(&mut self) -> MPR_W<'_>

Bit 5 - Magic packet received

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 6 - Wakeup frame received

pub fn gu(&mut self) -> GU_W<'_>

Bit 9 - Global unicast

pub fn wffrpr(&mut self) -> WFFRPR_W<'_>

Bit 31 - Wakeup frame filter register pointer reset

impl W<u32, Reg<u32, _MACSR>>

pub fn pmts(&mut self) -> PMTS_W<'_>

Bit 3 - PMT status

pub fn mmcs(&mut self) -> MMCS_W<'_>

Bit 4 - MMC status

pub fn mmcrs(&mut self) -> MMCRS_W<'_>

Bit 5 - MMC receive status

pub fn mmcts(&mut self) -> MMCTS_W<'_>

Bit 6 - MMC transmit status

pub fn tsts(&mut self) -> TSTS_W<'_>

Bit 9 - Time stamp trigger status

impl W<u32, Reg<u32, _MACIMR>>

pub fn pmtim(&mut self) -> PMTIM_W<'_>

Bit 3 - PMT interrupt mask

pub fn tstim(&mut self) -> TSTIM_W<'_>

Bit 9 - Time stamp trigger interrupt mask

impl W<u32, Reg<u32, _MACA0HR>>

pub fn maca0h(&mut self) -> MACA0H_W<'_>

Bits 0:15 - MAC address0 high

impl W<u32, Reg<u32, _MACA0LR>>

pub fn maca0l(&mut self) -> MACA0L_W<'_>

Bits 0:31 - MAC address0 low

impl W<u32, Reg<u32, _MACA1HR>>

pub fn maca1h(&mut self) -> MACA1H_W<'_>

Bits 0:15 - MAC address1 high

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA1LR>>

pub fn maca1l(&mut self) -> MACA1L_W<'_>

Bits 0:31 - MAC address1 low

impl W<u32, Reg<u32, _MACA2HR>>

pub fn maca2h(&mut self) -> MACA2H_W<'_>

Bits 0:15 - Ethernet MAC address 2 high register

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA2LR>>

pub fn maca2l(&mut self) -> MACA2L_W<'_>

Bits 0:30 - MAC address2 low

impl W<u32, Reg<u32, _MACA3HR>>

pub fn maca3h(&mut self) -> MACA3H_W<'_>

Bits 0:15 - MAC address3 high

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - Mask byte control

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - Source address

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - Address enable

impl W<u32, Reg<u32, _MACA3LR>>

pub fn maca3l(&mut self) -> MACA3L_W<'_>

Bits 0:31 - MAC address3 low

impl W<u32, Reg<u32, _MMCCR>>

pub fn cr(&mut self) -> CR_W<'_>

Bit 0 - Counter reset

pub fn csr(&mut self) -> CSR_W<'_>

Bit 1 - Counter stop rollover

pub fn ror(&mut self) -> ROR_W<'_>

Bit 2 - Reset on read

pub fn mcf(&mut self) -> MCF_W<'_>

Bit 31 - MMC counter freeze

impl W<u32, Reg<u32, _MMCRIR>>

pub fn rfces(&mut self) -> RFCES_W<'_>

Bit 5 - Received frames CRC error status

pub fn rfaes(&mut self) -> RFAES_W<'_>

Bit 6 - Received frames alignment error status

pub fn rgufs(&mut self) -> RGUFS_W<'_>

Bit 17 - Received good Unicast frames status

impl W<u32, Reg<u32, _MMCTIR>>

pub fn tgfscs(&mut self) -> TGFSCS_W<'_>

Bit 14 - Transmitted good frames single collision status

pub fn tgfmscs(&mut self) -> TGFMSCS_W<'_>

Bit 15 - Transmitted good frames more than single collision status

pub fn tgfs(&mut self) -> TGFS_W<'_>

Bit 21 - Transmitted good frames status

impl W<u32, Reg<u32, _MMCRIMR>>

pub fn rfcem(&mut self) -> RFCEM_W<'_>

Bit 5 - Received frame CRC error mask

pub fn rfaem(&mut self) -> RFAEM_W<'_>

Bit 6 - Received frames alignment error mask

pub fn rgufm(&mut self) -> RGUFM_W<'_>

Bit 17 - Received good Unicast frames mask

impl W<u32, Reg<u32, _MMCTIMR>>

pub fn tgfscm(&mut self) -> TGFSCM_W<'_>

Bit 14 - Transmitted good frames single collision mask

pub fn tgfmscm(&mut self) -> TGFMSCM_W<'_>

Bit 15 - Transmitted good frames more than single collision mask

pub fn tgfm(&mut self) -> TGFM_W<'_>

Bit 21 - Transmitted good frames mask

impl W<u32, Reg<u32, _PTPTSCR>>

pub fn tse(&mut self) -> TSE_W<'_>

Bit 0 - Time stamp enable

pub fn tsfcu(&mut self) -> TSFCU_W<'_>

Bit 1 - Time stamp fine or coarse update

pub fn tssti(&mut self) -> TSSTI_W<'_>

Bit 2 - Time stamp system time initialize

pub fn tsstu(&mut self) -> TSSTU_W<'_>

Bit 3 - Time stamp system time update

pub fn tsite(&mut self) -> TSITE_W<'_>

Bit 4 - Time stamp interrupt trigger enable

pub fn tsaru(&mut self) -> TSARU_W<'_>

Bit 5 - Time stamp addend register update

impl W<u32, Reg<u32, _PTPSSIR>>

pub fn stssi(&mut self) -> STSSI_W<'_>

Bits 0:7 - System time subsecond increment

impl W<u32, Reg<u32, _PTPTSHUR>>

pub fn tsus(&mut self) -> TSUS_W<'_>

Bits 0:31 - Time stamp update second

impl W<u32, Reg<u32, _PTPTSLUR>>

pub fn tsuss(&mut self) -> TSUSS_W<'_>

Bits 0:30 - Time stamp update subseconds

pub fn tsupns(&mut self) -> TSUPNS_W<'_>

Bit 31 - Time stamp update positive or negative sign

impl W<u32, Reg<u32, _PTPTSAR>>

pub fn tsa(&mut self) -> TSA_W<'_>

Bits 0:31 - Time stamp addend

impl W<u32, Reg<u32, _PTPTTHR>>

pub fn ttsh(&mut self) -> TTSH_W<'_>

Bits 0:31 - Target time stamp high

impl W<u32, Reg<u32, _PTPTTLR>>

pub fn ttsl(&mut self) -> TTSL_W<'_>

Bits 0:31 - Target time stamp low

impl W<u32, Reg<u32, _DMABMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 0 - Software reset

pub fn da(&mut self) -> DA_W<'_>

Bit 1 - DMA arbitration

pub fn dsl(&mut self) -> DSL_W<'_>

Bits 2:6 - Descriptor skip length

pub fn pbl(&mut self) -> PBL_W<'_>

Bits 8:13 - Programmable burst length

pub fn pm(&mut self) -> PM_W<'_>

Bits 14:15 - Rx-Tx priority ratio

pub fn fb(&mut self) -> FB_W<'_>

Bit 16 - Fixed burst

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 17:22 - Rx DMA PBL

pub fn usp(&mut self) -> USP_W<'_>

Bit 23 - Use separate PBL

pub fn fpm(&mut self) -> FPM_W<'_>

Bit 24 - 4xPBL mode

pub fn aab(&mut self) -> AAB_W<'_>

Bit 25 - Address-aligned beats

impl W<u32, Reg<u32, _DMATPDR>>

pub fn tpd(&mut self) -> TPD_W<'_>

Bits 0:31 - Transmit poll demand

impl W<u32, Reg<u32, _DMARPDR>>

pub fn rpd(&mut self) -> RPD_W<'_>

Bits 0:31 - Receive poll demand

impl W<u32, Reg<u32, _DMARDLAR>>

pub fn srl(&mut self) -> SRL_W<'_>

Bits 0:31 - Start of receive list

impl W<u32, Reg<u32, _DMATDLAR>>

pub fn stl(&mut self) -> STL_W<'_>

Bits 0:31 - Start of transmit list

impl W<u32, Reg<u32, _DMASR>>

pub fn ts(&mut self) -> TS_W<'_>

Bit 0 - Transmit status

pub fn tpss(&mut self) -> TPSS_W<'_>

Bit 1 - Transmit process stopped status

pub fn tbus(&mut self) -> TBUS_W<'_>

Bit 2 - Transmit buffer unavailable status

pub fn tjts(&mut self) -> TJTS_W<'_>

Bit 3 - Transmit jabber timeout status

pub fn ros(&mut self) -> ROS_W<'_>

Bit 4 - Receive overflow status

pub fn tus(&mut self) -> TUS_W<'_>

Bit 5 - Transmit underflow status

pub fn rs(&mut self) -> RS_W<'_>

Bit 6 - Receive status

pub fn rbus(&mut self) -> RBUS_W<'_>

Bit 7 - Receive buffer unavailable status

pub fn rpss(&mut self) -> RPSS_W<'_>

Bit 8 - Receive process stopped status

pub fn pwts(&mut self) -> PWTS_W<'_>

Bit 9 - Receive watchdog timeout status

pub fn ets(&mut self) -> ETS_W<'_>

Bit 10 - Early transmit status

pub fn fbes(&mut self) -> FBES_W<'_>

Bit 13 - Fatal bus error status

pub fn ers(&mut self) -> ERS_W<'_>

Bit 14 - Early receive status

pub fn ais(&mut self) -> AIS_W<'_>

Bit 15 - Abnormal interrupt summary

pub fn nis(&mut self) -> NIS_W<'_>

Bit 16 - Normal interrupt summary

impl W<u32, Reg<u32, _DMAOMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 1 - Start/stop receive

pub fn osf(&mut self) -> OSF_W<'_>

Bit 2 - Operate on second frame

pub fn rtc(&mut self) -> RTC_W<'_>

Bits 3:4 - Receive threshold control

pub fn fugf(&mut self) -> FUGF_W<'_>

Bit 6 - Forward undersized good frames

pub fn fef(&mut self) -> FEF_W<'_>

Bit 7 - Forward error frames

pub fn st(&mut self) -> ST_W<'_>

Bit 13 - Start/stop transmission

pub fn ttc(&mut self) -> TTC_W<'_>

Bits 14:16 - Transmit threshold control

pub fn ftf(&mut self) -> FTF_W<'_>

Bit 20 - Flush transmit FIFO

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 21 - Transmit store and forward

pub fn dfrf(&mut self) -> DFRF_W<'_>

Bit 24 - Disable flushing of received frames

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 25 - Receive store and forward

pub fn dtcefd(&mut self) -> DTCEFD_W<'_>

Bit 26 - Dropping of TCP/IP checksum error frames disable

impl W<u32, Reg<u32, _DMAIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 0 - Transmit interrupt enable

pub fn tpsie(&mut self) -> TPSIE_W<'_>

Bit 1 - Transmit process stopped interrupt enable

pub fn tbuie(&mut self) -> TBUIE_W<'_>

Bit 2 - Transmit buffer unavailable interrupt enable

pub fn tjtie(&mut self) -> TJTIE_W<'_>

Bit 3 - Transmit jabber timeout interrupt enable

pub fn roie(&mut self) -> ROIE_W<'_>

Bit 4 - Receive overflow interrupt enable

pub fn tuie(&mut self) -> TUIE_W<'_>

Bit 5 - Transmit underflow interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 6 - Receive interrupt enable

pub fn rbuie(&mut self) -> RBUIE_W<'_>

Bit 7 - Receive buffer unavailable interrupt enable

pub fn rpsie(&mut self) -> RPSIE_W<'_>

Bit 8 - Receive process stopped interrupt enable

pub fn rwtie(&mut self) -> RWTIE_W<'_>

Bit 9 - Receive watchdog timeout interrupt enable

pub fn etie(&mut self) -> ETIE_W<'_>

Bit 10 - Early transmit interrupt enable

pub fn fbeie(&mut self) -> FBEIE_W<'_>

Bit 13 - Fatal bus error interrupt enable

pub fn erie(&mut self) -> ERIE_W<'_>

Bit 14 - Early receive interrupt enable

pub fn aise(&mut self) -> AISE_W<'_>

Bit 15 - Abnormal interrupt summary enable

pub fn nise(&mut self) -> NISE_W<'_>

Bit 16 - Normal interrupt summary enable

impl W<u32, Reg<u32, _FS_GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _FS_GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _FS_GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _FS_GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 7 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _FS_GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _FS_GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _FS_GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _FS_GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_DEVICE>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _FS_GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _FS_CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _FS_HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _FS_HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _FS_HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _FS_HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _FS_HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _FS_HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _FS_HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _FS_HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _FS_DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _FS_DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _FS_DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _FS_DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _FS_DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _FS_DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _FS_PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 8 - DBG_IWDG_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 9 - DBG_WWDG_STOP

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 10 - DBG_TIM1_STOP

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 11 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 12 - DBG_TIM3_STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 13 - DBG_TIM4_STOP

pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<'_>

Bit 14 - DBG_CAN1_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 15 - DBG_I2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 16 - DBG_I2C2_SMBUS_TIMEOUT

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 18 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 19 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 20 - DBG_TIM7_STOP

pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<'_>

Bit 21 - DBG_CAN2_STOP

impl W<u32, Reg<u32, _SR>>

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - DR

impl W<u32, Reg<u32, _BRR>>

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - DIV_Fraction

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - DIV_Mantissa

impl W<u32, Reg<u32, _CR1>>

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Reset bit

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - Prefetch buffer enable

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash Address

impl W<u32, Reg<u32, _BCR1>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR1>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR2>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR2>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR3>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR3>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR4>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR4>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _PCR2>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR2>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM2>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT2>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - Attribute memory x databus HiZ time

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - Attribute memory x hold time

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - Attribute memory x wait time

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - Attribute memory x setup time

impl W<u32, Reg<u32, _PCR3>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR3>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM3>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT3>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR4>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR4>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM4>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT4>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PIO4>>

pub fn iohizx(&mut self) -> IOHIZX_W<'_>

Bits 24:31 - IOHIZx

pub fn ioholdx(&mut self) -> IOHOLDX_W<'_>

Bits 16:23 - IOHOLDx

pub fn iowaitx(&mut self) -> IOWAITX_W<'_>

Bits 8:15 - IOWAITx

pub fn iosetx(&mut self) -> IOSETX_W<'_>

Bits 0:7 - IOSETx

impl W<u32, Reg<u32, _BWTR1>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR2>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR3>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR4>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 15:18 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 15:18 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn ep_id(&mut self) -> EP_ID_W<'_>

Bits 0:3 - Endpoint Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction of transaction

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

pub fn ctr(&mut self) -> CTR_W<'_>

Bit 15 - Correct transfer

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _ACTRL>>

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD_>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

impl W<u32, Reg<u32, _JOFR1>>

pub fn joffset1(&mut self) -> JOFFSET1_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR2>>

pub fn joffset2(&mut self) -> JOFFSET2_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR3>>

pub fn joffset3(&mut self) -> JOFFSET3_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _JOFR4>>

pub fn joffset4(&mut self) -> JOFFSET4_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence