Struct RegisterBlock 

pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn cr(&self) -> &Reg<CRrs>

0x00 - Control register (DAC_CR)

pub const fn swtrigr(&self) -> &Reg<SWTRIGRrs>

0x04 - DAC software trigger register (DAC_SWTRIGR)

pub const fn dhr12r(&self, n: usize) -> &Reg<DHR12Rrs>

0x08..0x10 - channel%s 12-bit right-aligned data holding register

`n` is the index of register in the array. `n == 0` corresponds to `DHR12R1` register.

pub fn dhr12r_iter(&self) -> impl Iterator<Item = &Reg<DHR12Rrs>>

Iterator for array of: 0x08..0x10 - channel%s 12-bit right-aligned data holding register

pub const fn dhr12r1(&self) -> &Reg<DHR12Rrs>

0x08 - channel1 12-bit right-aligned data holding register

pub const fn dhr12r2(&self) -> &Reg<DHR12Rrs>

0x14 - channel2 12-bit right-aligned data holding register

pub const fn dhr12l(&self, n: usize) -> &Reg<DHR12Lrs>

0x0c..0x14 - channel%s 12-bit left aligned data holding register

`n` is the index of register in the array. `n == 0` corresponds to `DHR12L1` register.

pub fn dhr12l_iter(&self) -> impl Iterator<Item = &Reg<DHR12Lrs>>

Iterator for array of: 0x0c..0x14 - channel%s 12-bit left aligned data holding register

pub const fn dhr12l1(&self) -> &Reg<DHR12Lrs>

0x0c - channel1 12-bit left aligned data holding register

pub const fn dhr12l2(&self) -> &Reg<DHR12Lrs>

0x18 - channel2 12-bit left aligned data holding register

pub const fn dhr8r(&self, n: usize) -> &Reg<DHR8Rrs>

0x10..0x18 - channel%s 8-bit right aligned data holding register

`n` is the index of register in the array. `n == 0` corresponds to `DHR8R1` register.

pub fn dhr8r_iter(&self) -> impl Iterator<Item = &Reg<DHR8Rrs>>

Iterator for array of: 0x10..0x18 - channel%s 8-bit right aligned data holding register

pub const fn dhr8r1(&self) -> &Reg<DHR8Rrs>

0x10 - channel1 8-bit right aligned data holding register

pub const fn dhr8r2(&self) -> &Reg<DHR8Rrs>

0x1c - channel2 8-bit right aligned data holding register

pub const fn dhr12rd(&self) -> &Reg<DHR12RDrs>

0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

pub const fn dhr12ld(&self) -> &Reg<DHR12LDrs>

0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

pub const fn dhr8rd(&self) -> &Reg<DHR8RDrs>

0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

pub const fn dor(&self, n: usize) -> &Reg<DORrs>

0x2c..0x34 - channel%s data output register

`n` is the index of register in the array. `n == 0` corresponds to `DOR1` register.

pub fn dor_iter(&self) -> impl Iterator<Item = &Reg<DORrs>>

Iterator for array of: 0x2c..0x34 - channel%s data output register

pub const fn dor1(&self) -> &Reg<DORrs>

0x2c - channel1 data output register

pub const fn dor2(&self) -> &Reg<DORrs>

0x30 - channel2 data output register

Trait Implementations

impl Debug for RegisterBlock

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.