Enum stm32f0xx_hal::stm32::tim3::ccmr2_output::OC4PE_A [−][src]
pub enum OC4PE_A {
DISABLED,
ENABLED,
}
Expand description
Output compare 4 preload enable
Value on reset: 0
Variants
0: Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
1: Preload register on CCR4 enabled. Preload value is loaded into active register on each update event