Struct Spi

pub struct Spi<R> {
    pub regs: R,
    pub cfg: SpiConfig,
}

Represents a Serial Peripheral Interface (SPI) peripheral.

Fields

regs: R

cfg: SpiConfig

Implementations

impl<R> Spi<R>

where R: Deref<Target = RegisterBlock> + RccPeriph,

pub fn new(regs: R, cfg: SpiConfig, baud_rate: BaudRate) -> Self

Initialize an SPI peripheral, including configuration register writes, and enabling and resetting its RCC peripheral clock.

pub fn reclock(&mut self, baud_rate: BaudRate)

Change the SPI baud rate.

pub fn disable(&mut self) -> Result<()>

L44 RM, section 40.4.9: “Procedure for disabling the SPI” When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. It is important to do this before the system enters a low-power mode when the peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some modes the disable procedure is the only way to stop continuous communication running.

pub fn read(&mut self) -> Result<u8>

Read a single byte if available, or block until it’s available.

pub fn write_one(&mut self, byte: u8) -> Result<()>

Write a single byte if available, or block until it’s available. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn write(&mut self, words: &[u8]) -> Result<()>

Write multiple bytes on the SPI line, blocking until complete. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<()>

Read multiple bytes to a buffer, blocking until complete. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn transfer_type2<'w>( &mut self, write_buf: &'w [u8], read_buf: &'w mut [u8], ) -> Result<()>

An alternative transfer API, using separate read and write buffers.

pub unsafe fn read_dma( &mut self, buf: &mut [u8], channel: DmaChannel, channel_cfg: ChannelCfg, dma_periph: DmaPeriph, ) -> Result<()>

Receive data using DMA. See L44 RM, section 40.4.9: Communication using DMA. Note that the channel argument is unused on F3 and L4, since it is hard-coded, and can’t be configured using the DMAMUX peripheral. (dma::mux() fn).

pub unsafe fn write_dma( &mut self, buf: &[u8], channel: DmaChannel, channel_cfg: ChannelCfg, dma_periph: DmaPeriph, ) -> Result<()>

Transmit data using DMA. See L44 RM, section 40.4.9: Communication using DMA. Note that the channel argument is unused on F3 and L4, since it is hard-coded, and can’t be configured using the DMAMUX peripheral. (dma::mux() fn).

pub unsafe fn transfer_dma( &mut self, buf_write: &[u8], buf_read: &mut [u8], channel_write: DmaChannel, channel_read: DmaChannel, channel_cfg_write: ChannelCfg, channel_cfg_read: ChannelCfg, dma_periph: DmaPeriph, ) -> Result<()>

Transfer data from DMA; this is the basic reading API, using both write and read transfers: It performs a write with register data, and reads to a buffer.

pub fn enable_interrupt(&mut self, interrupt_type: SpiInterrupt)

Enable an interrupt. Note that unlike on other peripherals, there’s no explicit way to clear these. RM: “Writing to the transmit data register always clears the TXE bit. The TXE flag is set by hardware.”

impl<R> Spi<R>

where R: Deref<Target = RegisterBlock> + RccPeriph,

pub fn stop_dma( &mut self, channel: DmaChannel, channel2: Option<DmaChannel>, dma_periph: DmaPeriph, ) -> Result<()>

Stop a DMA transfer. Stops the channel, and disables the txdmaen and rxdmaen bits. Run this after each transfer completes - you may wish to do this in an interrupt (eg DMA transfer complete) instead of blocking. channel2 is an optional second channel to stop; eg if you have both a tx and rx channel.

pub fn cleanup_dma( &mut self, dma_periph: DmaPeriph, channel_tx: DmaChannel, channel_rx: Option<DmaChannel>, ) -> Result<()>

Convenience function that clears the interrupt, and stops the transfer. For use with the TC interrupt only.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.