Struct SaiConfig 

pub struct SaiConfig {

    pub mode: SaiMode,
    pub protocol: Protocol,
    pub mono: Mono,
    pub sync: SyncMode,
    pub sync_out: SyncOut,
    pub sync_in: SyncIn,
    pub clock_strobe: ClockStrobe,
    pub datasize: DataSize,
    pub slotsize: SlotSize,
    pub master_clock: MasterClock,
    pub first_bit: FirstBit,
    pub oversampling_ratio: OversamplingRatio,
    pub frame_length: u16,
    pub fs_offset: FsOffset,
    pub fs_polarity: FsPolarity,
    pub fs_signal: FsSignal,
    pub num_slots: u8,
    pub fifo_thresh: FifoThresh,
    pub first_bit_offset: u8,
    pub pdm_mode: bool,
    pub num_pdm_mics: NumPdmMics,
    pub pdm_clock_used: u8,
    pub mckdiv: u8,
}

Configuration for the SAI peripheral. Mainly affects the ACR and BCR registers. Used for either channel. For details, see documentation of individual structs and fields. You may be forced into certain settings based on the device used.

Fields

mode: SaiMode

protocol: Protocol

Select protocols between Free, Ac’97, and SPDIF. Defaults to Free.

mono: Mono

Select mono or stereo modes. Default to mono.

sync: SyncMode

An audio subblock can be configured to operate synchronously with the second audio subblock in the same SAI. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication. Default to async.

sync_out: SyncOut

Used for synchronization with other SAI blocks and peripherals. Set this using the A config. Controls which block is the master synchronization signal for other SAI peripherals.

sync_in: SyncIn

Used for synchronization with other SAI blocks and peripherals. Set this using the A config. Configurd to sync with SAI1, if syncmode is external.

clock_strobe: ClockStrobe

Clock strobing edge. Defaults to Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge

datasize: DataSize

Size of the data in the slot. Defaults to 24-bit.

slotsize: SlotSize

Size of the slot; can be 16 or 32 bits. Defaults to the same or larger for the data size.

master_clock: MasterClock

Select wheather the master clock out is enabled, eg for syncing external devices. Defaults to disabled.

first_bit: FirstBit

oversampling_ratio: OversamplingRatio

frame_length: u16

Define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NOMCK = 1), it is recommended to program the frame length to an value ranging from 8 to 256.

fs_offset: FsOffset

fs_polarity: FsPolarity

Active high, or active low polarity. Defaults to active high.

fs_signal: FsSignal

Start of frame. Default to frame and channel.

num_slots: u8

Number of slots. Defaults to 2.

fifo_thresh: FifoThresh

The FIFO threshold configures when the FREQ interrupt is generated based on how full the FIFO is.

first_bit_offset: u8

These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC’97 or SPDIF mode.

pdm_mode: bool

Enable Pulse Density Modulation (PDM) functionality, eg for digital microphones. See the relevant ST Application note: AN5027

num_pdm_mics: NumPdmMics

The number of connected PDM mics, if applicable. Defualts to 2.

pdm_clock_used: u8

Which PDM CK line to enable. Must be 1-4. Defaults to 1. (CK1 in User manuals)

mckdiv: u8

Master clock divider. Divides the kernel clock input. Defaults to 0, for no division.

Implementations

impl SaiConfig

pub fn i2s_preset() -> Self

Default configuration for I2S.

pub fn tdm_preset(num_slots: u8, slotsize: SlotSize) -> Self

Default configuration for TDM. Configures an I2S-style delay of 1 between FS and data start. Configures the FS signal to be a pulse indicating frame start. Sets window length based on data size and number of slots.

pub fn pdm_mic_preset(num_mics: NumPdmMics, clock_used: u8) -> Self

Default configuration for PDM microphones. See H743 RM, Table 422. TDM settings. See table 423 for how to configure Frame Length, and number of slots. This default configures for 48kHz sample rate, assuming 3.072Mhz SAI clock, and 1 slots of 16 bits per frame. If using something else, see Table 423, and modify as required.

pub fn ac97_preset() -> Self

Default configuration for AC’97

pub fn spdif_preset() -> Self

Default configuration for SPDIF

Trait Implementations

impl Clone for SaiConfig

fn clone(&self) -> SaiConfig

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for SaiConfig

fn default() -> Self

Returns the “default value” for a type.