Module clocks

This module contains clock configurations for various MCUs. They tend to be significantly different from one another, so we’ve feature-gated these files, rather than code within the files, to differentiate families. This documentation is built for H723, and will not be correct for other variants. For F series defaults, check out the Default impl here. Check here for other H7 variants For other STM32 families, look here.

Alternatively, you can examine the CLocks structure to see which scalers are set, or generate docs locally for your variant.//!

See STM32CubeIDE for an interactive editor that’s very useful for seeing what settings are available, and validating them.

See the Reference Manuals for non-interactive visualizations.

Structs

Clocks

Settings used to configure clocks. Create this struct by using its Default::default() implementation, then modify as required, referencing your RM’s clock tree, or Stm32Cube IDE’s interactive clock manager. Apply settings by running .setup().

PllCfg

Configures the speeds, and enable status of an individual PLL (PLL1, or SAIPLL). Note that the enable field has no effect for PLL1.

Enums

ApbPrescaler

For use with RCC_APBPPRE1, and RCC_APBPPRE2. Ie, low-speed and high-speed prescalers respectively.

CanSrc

CAN clock input source. Sets RCC_CCIPR register, FDCANSEL field.

Clk48Src

CrsSyncSrc

Select the SYNC signal source. Sets the CRS_CFGR register, SYNCSRC field.

HclkPrescaler

Division factor for the AHB clock. Also known as AHB Prescaler. L4 RM, 6.4.3 on WB, used for all 3 HCLK prescalers.

InputSrc

LpUartSrc

LpUart clock sources. Defaults to Pclk.

PllSrc

Pllm

Pllp

Divisor for PLLP. Sets PLLCFGR reg, PLLP field.

Pllr

Main PLL division factor for PLLCLK (system clock). G4 RM 7.4.4. Also used to set PLLQ.

RccError

Speed out of limits.

SaiSrc

SAI clock input source. Sets RCC_CCIPR register, SAIxSEL fields.

Functions

enable_crs

Enable the Clock Recovery System. L443 User manual: “The STM32L443xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.” Note: This is for HSI48 only. Note that the HSI will turn off after entering Stop or Standby.