#[repr(u8)]pub enum Pllr {
Div2 = 0,
Div4 = 1,
Div6 = 2,
Div8 = 3,
}
Expand description
Main PLL division factor for PLLCLK (system clock). G4 RM 7.4.4. Also used to set PLLQ.
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Auto Trait Implementations§
impl Freeze for Pllr
impl RefUnwindSafe for Pllr
impl Send for Pllr
impl Sync for Pllr
impl Unpin for Pllr
impl UnwindSafe for Pllr
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Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more