Struct Timer

pub struct Timer<TIM> {
    pub regs: TIM,
    pub cfg: TimerConfig,
    /* private fields */
}

Represents a General Purpose or Advanced Control timer.

Fields

regs: TIM

Register block for the specific timer.

cfg: TimerConfig

Our config stucture, for configuration that is written to the timer hardware on initialization via the constructor.

Implementations

impl Timer<TIM1>

pub fn new_tim1( regs: TIM1, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u16

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM1>

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u16

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u16)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM2>

pub fn new_tim2( regs: TIM2, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u32

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM2>

pub fn set_dir(&mut self)

Function that allows us to set direction only on timers that have this option.

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u32

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u32)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_alignment(&mut self, alignment: Alignment)

Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM3>

pub fn new_tim3( regs: TIM3, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u32

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM3>

pub fn set_dir(&mut self)

Function that allows us to set direction only on timers that have this option.

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u32

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u32)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_alignment(&mut self, alignment: Alignment)

Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM4>

pub fn new_tim4( regs: TIM4, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u32

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM4>

pub fn set_dir(&mut self)

Function that allows us to set direction only on timers that have this option.

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u32

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u32)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_alignment(&mut self, alignment: Alignment)

Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM8>

pub fn new_tim8( regs: TIM8, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u32

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM8>

pub fn set_dir(&mut self)

Function that allows us to set direction only on timers that have this option.

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u32

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u32)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_alignment(&mut self, alignment: Alignment)

Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM15>

pub fn new_tim15( regs: TIM15, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u16

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM15>

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u16

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u16)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM16>

pub fn new_tim16( regs: TIM16, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u16

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM16>

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u16

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u16)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.

impl Timer<TIM17>

pub fn new_tim17( regs: TIM17, freq: f32, cfg: TimerConfig, clocks: &Clocks, ) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable_interrupt(&mut self, interrupt: TimerInterrupt)

Enable a specific type of Timer interrupt.

pub fn disable_interrupt(&mut self, interrupt: TimerInterrupt)

Disable a specific type of Timer interrupt.

pub fn clear_interrupt(&mut self, interrupt: TimerInterrupt)

Clears interrupt associated with this timer.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.

pub fn enable(&mut self)

Enable (start) the timer.

pub fn disable(&mut self)

Disable (stop) the timer.

pub fn is_enabled(&self) -> bool

Check if the timer is enabled.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

pub fn set_freq(&mut self, freq: f32) -> Result<(), ValueError>

Set the timer frequency, in Hz. Overrides the period or frequency set in the constructor.

pub fn set_period(&mut self, period: f32) -> Result<(), ValueError>

Set the timer period, in seconds. Overrides the period or frequency set in the constructor.

pub fn set_auto_reload(&mut self, arr: u32)

Set the auto-reload register value. Used for adjusting frequency.

pub fn set_prescaler(&mut self, psc: u16)

Set the prescaler value. Used for adjusting frequency.

pub fn reset_count(&mut self)

Reset the countdown; set the counter to 0.

pub fn get_uif(&self) -> bool

UIF Flag in SR register is set when CNT reg is overflow / underflow

pub fn clear_uif(&mut self)

pub fn reinitialize(&mut self)

Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. When changing timer frequency (or period) via PSC, you may need to run this. Alternatively, change the freq in an update ISR. Note from RM, PSC reg: PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).’ If you’re doing something where the updates can wait a cycle, this isn’t required. (eg PWM with changing duty period).

pub fn read_count(&self) -> u32

Read the current counter value.

pub fn enable_pwm_output( &mut self, channel: TimChannel, compare: OutputCompare, duty: f32, )

Enables PWM output for a given channel and output compare, with an initial duty cycle, in Hz.

pub fn get_max_duty(&self) -> u16

Return the integer associated with the maximum duty period.

pub unsafe fn write_dma_burst( &mut self, buf: &[u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

See G4 RM, section 29.4.24: Dma burst mode. “The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.” This may be used to create arbitrary waveforms by modifying the CCR register (base address = 13-16, for CCR1-4), or for implementing duty-cycle based digital protocols.

pub unsafe fn read_dma_burst( &mut self, buf: &mut [u16], base_address: u8, burst_len: u8, dma_channel: DmaChannel, channel_cfg: ChannelCfg, ds_32_bits: bool, dma_periph: DmaPeriph, )

pub fn now(&mut self) -> Instant

Get the time elapsed since the start of the timer, taking overflow wraps into account.

Important: the value returned here will only be correct if the ARR and PSC are set only using the constructor, set_freq, or set_period methods.

pub fn elapsed(&mut self, since: Instant) -> Duration

impl Timer<TIM17>

pub fn set_input_capture( &mut self, channel: TimChannel, mode: CaptureCompare, ccp: Polarity, ccnp: Polarity, )

Set up input capture, eg for PWM input. L4 RM, section 26.3.8. H723 RM, section 43.3.7. Note: Does not handle TISEL (timer input selection register - you must do this manually using the PAC.

pub fn set_output_compare(&mut self, channel: TimChannel, mode: OutputCompare)

Set Output Compare Mode. See docs on the OutputCompare enum.

pub fn get_duty(&self, channel: TimChannel) -> u16

Return the set duty period for a given channel. Divide by get_max_duty() to find the portion of the duty cycle used.

pub fn set_duty(&mut self, channel: TimChannel, duty: u16)

Set the duty cycle, as a portion of ARR (get_max_duty()). Note that this needs to be re-run if you change ARR at any point.

pub fn set_polarity(&mut self, channel: TimChannel, polarity: Polarity)

Set output polarity. See docs on the Polarity enum.

pub fn set_complementary_polarity( &mut self, channel: TimChannel, polarity: Polarity, )

Set complementary output polarity. See docs on the Polarity enum.

pub fn disable_capture_compare(&mut self, channel: TimChannel)

Disables capture compare on a specific channel.

pub fn enable_capture_compare(&mut self, channel: TimChannel)

Enables capture compare on a specific channel.

pub fn set_capture_compare_output( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in output mode. See docs on the CaptureCompare enum.

pub fn set_capture_compare_input( &mut self, channel: TimChannel, mode: CaptureCompare, )

Set Capture Compare mode in input mode. See docs on the CaptureCompare enum.

pub fn set_preload(&mut self, channel: TimChannel, value: bool)

Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Setting preload is required to enable PWM.