pub struct W(/* private fields */);
Expand description
Register TIMINGR
writer
Implementations§
source§impl W
impl W
sourcepub fn scll(
&mut self
) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 8, 0>
pub fn scll( &mut self ) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 8, 0>
Bits 0:7 - SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings.
sourcepub fn sclh(
&mut self
) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 8, 8>
pub fn sclh( &mut self ) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 8, 8>
Bits 8:15 - SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing.
sourcepub fn sdadel(
&mut self
) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 4, 16>
pub fn sdadel( &mut self ) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 4, 16>
Bits 16:19 - Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing.
sourcepub fn scldel(
&mut self
) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 4, 20>
pub fn scldel( &mut self ) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 4, 20>
Bits 20:23 - Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing.
sourcepub fn presc(
&mut self
) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 4, 28>
pub fn presc( &mut self ) -> FieldWriterRaw<'_, u32, TIMINGR_SPEC, u8, u8, Safe, 4, 28>
Bits 28:31 - Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK
Methods from Deref<Target = W<TIMINGR_SPEC>>§
sourcepub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.