Struct stm32_hal2::pac::gpioa::lckr::R

pub struct R(/* private fields */);

Register LCKR reader

Implementations

impl R

pub fn lck0(&self) -> BitReaderRaw<LCK0_A>

Bit 0 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck1(&self) -> BitReaderRaw<LCK0_A>

Bit 1 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck2(&self) -> BitReaderRaw<LCK0_A>

Bit 2 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck3(&self) -> BitReaderRaw<LCK0_A>

Bit 3 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck4(&self) -> BitReaderRaw<LCK0_A>

Bit 4 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck5(&self) -> BitReaderRaw<LCK0_A>

Bit 5 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck6(&self) -> BitReaderRaw<LCK0_A>

Bit 6 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck7(&self) -> BitReaderRaw<LCK0_A>

Bit 7 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck8(&self) -> BitReaderRaw<LCK0_A>

Bit 8 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck9(&self) -> BitReaderRaw<LCK0_A>

Bit 9 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck10(&self) -> BitReaderRaw<LCK0_A>

Bit 10 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck11(&self) -> BitReaderRaw<LCK0_A>

Bit 11 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck12(&self) -> BitReaderRaw<LCK0_A>

Bit 12 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck13(&self) -> BitReaderRaw<LCK0_A>

Bit 13 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck14(&self) -> BitReaderRaw<LCK0_A>

Bit 14 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lck15(&self) -> BitReaderRaw<LCK0_A>

Bit 15 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

pub fn lckk(&self) -> BitReaderRaw<LCKK_A>

Bit 16 - Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset.

Methods from Deref<Target = R<LCKR_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<LCKR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<LCKR_SPEC>> for R

fn from(reader: R<LCKR_SPEC>) -> R

Converts to this type from the input type.