Struct stm32_hal2::pac::cryp::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 36 fields
    pub cr: Reg<CR_SPEC>,
    pub sr: Reg<SR_SPEC>,
    pub din: Reg<DIN_SPEC>,
    pub dout: Reg<DOUT_SPEC>,
    pub dmacr: Reg<DMACR_SPEC>,
    pub imscr: Reg<IMSCR_SPEC>,
    pub risr: Reg<RISR_SPEC>,
    pub misr: Reg<MISR_SPEC>,
    pub k0lr: Reg<K0LR_SPEC>,
    pub k0rr: Reg<K0RR_SPEC>,
    pub k1lr: Reg<K1LR_SPEC>,
    pub k1rr: Reg<K1RR_SPEC>,
    pub k2lr: Reg<K2LR_SPEC>,
    pub k2rr: Reg<K2RR_SPEC>,
    pub k3lr: Reg<K3LR_SPEC>,
    pub k3rr: Reg<K3RR_SPEC>,
    pub iv0lr: Reg<IV0LR_SPEC>,
    pub iv0rr: Reg<IV0RR_SPEC>,
    pub iv1lr: Reg<IV1LR_SPEC>,
    pub iv1rr: Reg<IV1RR_SPEC>,
    pub csgcmccm0r: Reg<CSGCMCCM0R_SPEC>,
    pub csgcmccm1r: Reg<CSGCMCCM1R_SPEC>,
    pub csgcmccm2r: Reg<CSGCMCCM2R_SPEC>,
    pub csgcmccm3r: Reg<CSGCMCCM3R_SPEC>,
    pub csgcmccm4r: Reg<CSGCMCCM4R_SPEC>,
    pub csgcmccm5r: Reg<CSGCMCCM5R_SPEC>,
    pub csgcmccm6r: Reg<CSGCMCCM6R_SPEC>,
    pub csgcmccm7r: Reg<CSGCMCCM7R_SPEC>,
    pub csgcm0r: Reg<CSGCM0R_SPEC>,
    pub csgcm1r: Reg<CSGCM1R_SPEC>,
    pub csgcm2r: Reg<CSGCM2R_SPEC>,
    pub csgcm3r: Reg<CSGCM3R_SPEC>,
    pub csgcm4r: Reg<CSGCM4R_SPEC>,
    pub csgcm5r: Reg<CSGCM5R_SPEC>,
    pub csgcm6r: Reg<CSGCM6R_SPEC>,
    pub csgcm7r: Reg<CSGCM7R_SPEC>,

}
Expand description

Register block

Fields§

§cr: Reg<CR_SPEC>

0x00 - control register

§sr: Reg<SR_SPEC>

0x04 - status register

§din: Reg<DIN_SPEC>

0x08 - data input register

§dout: Reg<DOUT_SPEC>

0x0c - data output register

§dmacr: Reg<DMACR_SPEC>

0x10 - DMA control register

§imscr: Reg<IMSCR_SPEC>

0x14 - interrupt mask set/clear register

§risr: Reg<RISR_SPEC>

0x18 - raw interrupt status register

§misr: Reg<MISR_SPEC>

0x1c - masked interrupt status register

§k0lr: Reg<K0LR_SPEC>

0x20 - key registers

§k0rr: Reg<K0RR_SPEC>

0x24 - key registers

§k1lr: Reg<K1LR_SPEC>

0x28 - key registers

§k1rr: Reg<K1RR_SPEC>

0x2c - key registers

§k2lr: Reg<K2LR_SPEC>

0x30 - key registers

§k2rr: Reg<K2RR_SPEC>

0x34 - key registers

§k3lr: Reg<K3LR_SPEC>

0x38 - key registers

§k3rr: Reg<K3RR_SPEC>

0x3c - key registers

§iv0lr: Reg<IV0LR_SPEC>

0x40 - Initialization vector register 0L

§iv0rr: Reg<IV0RR_SPEC>

0x44 - initialization vector register 0R

§iv1lr: Reg<IV1LR_SPEC>

0x48 - Initialization vector register 1L

§iv1rr: Reg<IV1RR_SPEC>

0x4c - Initialization vector register 1R

§csgcmccm0r: Reg<CSGCMCCM0R_SPEC>

0x50 - context swap register

§csgcmccm1r: Reg<CSGCMCCM1R_SPEC>

0x54 - context swap register

§csgcmccm2r: Reg<CSGCMCCM2R_SPEC>

0x58 - context swap register

§csgcmccm3r: Reg<CSGCMCCM3R_SPEC>

0x5c - context swap register

§csgcmccm4r: Reg<CSGCMCCM4R_SPEC>

0x60 - context swap register

§csgcmccm5r: Reg<CSGCMCCM5R_SPEC>

0x64 - context swap register

§csgcmccm6r: Reg<CSGCMCCM6R_SPEC>

0x68 - context swap register

§csgcmccm7r: Reg<CSGCMCCM7R_SPEC>

0x6c - context swap register

§csgcm0r: Reg<CSGCM0R_SPEC>

0x70 - context swap register

§csgcm1r: Reg<CSGCM1R_SPEC>

0x74 - context swap register

§csgcm2r: Reg<CSGCM2R_SPEC>

0x78 - context swap register

§csgcm3r: Reg<CSGCM3R_SPEC>

0x7c - context swap register

§csgcm4r: Reg<CSGCM4R_SPEC>

0x80 - context swap register

§csgcm5r: Reg<CSGCM5R_SPEC>

0x84 - context swap register

§csgcm6r: Reg<CSGCM6R_SPEC>

0x88 - context swap register

§csgcm7r: Reg<CSGCM7R_SPEC>

0x8c - context swap register

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