Enum stm32_hal2::timer::UpdateReqSrc

#[repr(u8)]
pub enum UpdateReqSrc {
    Any,
    OverUnderFlow,
}

Update Request source. This bit is set and cleared by software to select the UEV event sources. Sets TIMx_CR1 register, URS field.

Variants

Any

Any of the following events generate an update interrupt or DMA request. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller

OverUnderFlow

Only counter overflow/underflow generates an update interrupt or DMA request.

Trait Implementations

impl Clone for UpdateReqSrc

fn clone(&self) -> UpdateReqSrc

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for UpdateReqSrc