Struct stm32_hal2::pac::exti::cpuimr3::W

pub struct W(_);

Register CPUIMR3 writer

Implementations

impl W

pub fn mr64(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 0>

Bit 0 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr65(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 1>

Bit 1 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr66(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 2>

Bit 2 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr67(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 3>

Bit 3 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr68(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 4>

Bit 4 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr69(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 5>

Bit 5 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr70(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 6>

Bit 6 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr71(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 7>

Bit 7 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr72(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 8>

Bit 8 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr73(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 9>

Bit 9 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr74(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 10>

Bit 10 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr75(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 11>

Bit 11 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr76(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 12>

Bit 12 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr77(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 13>

Bit 13 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr78(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 14>

Bit 14 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr79(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 15>

Bit 15 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr80(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 16>

Bit 16 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr82(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 18>

Bit 18 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr84(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 20>

Bit 20 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr85(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 21>

Bit 21 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr86(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 22>

Bit 22 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr87(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 23>

Bit 23 - CPU Interrupt Mask on Direct Event input x+64

pub fn mr88(&mut self) -> BitWriterRaw<'_, u32, CPUIMR3_SPEC, MR64_A, BitM, 24>

Bit 24 - CPU Interrupt Mask on Direct Event input x+64

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CPUIMR3_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CPUIMR3_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CPUIMR3_SPEC>> for W

fn from(writer: W<CPUIMR3_SPEC>) -> W

Converts to this type from the input type.