Struct stm32_hal2::dfsdm::Dfsdm

pub struct Dfsdm<R> {
    pub regs: R,
    /* private fields */
}

Represents the Digital filter for sigma delta modulators (DFSDM) peripheral, for interfacing with external Σ∆ modulators.

Fields

regs: R

Implementations

impl<R> Dfsdm<R>where
R: Deref<Target = RegisterBlock>,

pub fn new(regs: R, config: DfsdmConfig, clock_cfg: &Clocks) -> Self

Initialize a DFSDM peripheral, including enabling and resetting its RCC peripheral clock.

pub fn enable(&mut self)

Enables the DFSDM peripheral. The DFSDM interface is globally enabled by setting DFSDMEN=1 in the CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7) and digital filters FLTx (x=0..3) start to work if their enable bits are set (channel enable bit CHEN in CHyCFGR1 and FLTx enable bit DFEN in FLTxCR1).

pub fn disable(&mut self)

Disables the DFSDM peripheral. DFSDM must be globally disabled (by DFSDMEN=0 in CH0CFGR1) before stopping the system clock to enter in the STOP mode of the device

pub fn enable_filter(&mut self, filter: Filter, channel: DfsdmChannel)

Configures and enables the DFSDM filter for a given channel, and enables that channel. Digital filter x FLTx (x=0..3) is enabled by setting DFEN=1 in the FLTxCR1 register. Once FLTx is enabled (DFEN=1), both Sincx digital filter unit and integrator unit are reinitialized. Note that this function sets DFEN, so run it after configuring other settings such as DMA.

pub fn disable_filter(&mut self, filter: Filter)

Disables the DFSDM peripheral. By clearing DFEN, any conversion which may be in progress is immediately stopped and FLTx is put into stop mode. All register settings remain unchanged except FLTxAWSR and FLTxISR (which are reset).

pub fn setup_pdm_mics(&mut self, channel: DfsdmChannel)

Configure for PDM microphone(s). Configures the left channel as the channel argument here, and the right channel as channel - 1. H742 RM, section 30.4.4

pub fn start_conversion(&self, filter: Filter)

Initiate a converssion. See H742 RM, section 30.4.15: Launching conversions

pub fn start_injected_conversion(&self, filter: Filter)

Initiate an injected conversion. See H742 RM, section 30.4.15: Launching conversions

pub fn read(&self, filter: Filter) -> i32

Read regular conversion data from the FLTxRDATAR register. Suitable for use after a conversion is complete. “Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction. The msb of output data word represents the sign of value (two’s complement format).”

See H742 RM, section 30.4.13: Data unitblock for details. “The right bit-shift of final data is performed in this module because the final data width is 24- bit and data coming from the processing path can be up to 32 bits. This right bit-shift is configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained - to have valid 24-bit signed format of result data. In the next step, an offset correction of the result is performed. The offset correction value (OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate calibration routine.”

pub fn read_injected(&self, filter: Filter) -> i32

Read injected conversion data from the FLTxJDATAR register. Suitable for use after a conversion is complete.

pub unsafe fn read_dma(
&mut self,
buf: &mut [i32],
filter: Filter,
dma_channel: DmaChannel,
channel_cfg: ChannelCfg,
dma_periph: DmaPeriph
)

Read data from SAI with DMA. H743 RM, section 30.6: DFSDM DMA transfer To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in FLTxCR1 register. Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or regular conversion (JEOCF or REOCF bit in FLTxISR register) because DMA is reading FLTxJDATAR or FLTxRDATAR register

Note that this reads the entire rdatar register into memory, not just the rdata field. You need to shift the result 8 bits to the result after reading the values from memory to discard the other fields. (The integer signing is unchanged, since the 24-bit integer data is aligned to the left of the 32-bit register, which maps to an i32 here.)

pub fn enable_interrupt(
&mut self,
interrupt_type: DfsdmInterrupt,
channel: Filter
)

Enable a specific type of interrupt. See H743 RM, section 30.5: DFSDM interrupts

pub fn clear_interrupt(&mut self, interrupt_type: DfsdmInterrupt, channel: Filter)

Clears the interrupt pending flag for a specific type of interrupt. Note that to clear EndofInjectedConversion, or EndOfConversion interrupt,s read the FLTxJDATAR or FLTxRDATAR registers respectively.