pub struct R(_);
Expand description
Register CLKCR
reader
Implementations
sourceimpl R
impl R
sourcepub fn clkdiv(&self) -> FieldReaderRaw<u16, u16>
pub fn clkdiv(&self) -> FieldReaderRaw<u16, u16>
Bits 0:9 - Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc..
sourcepub fn pwrsav(&self) -> BitReaderRaw<bool>
pub fn pwrsav(&self) -> BitReaderRaw<bool>
Bit 12 - Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:
sourcepub fn widbus(&self) -> FieldReaderRaw<u8, u8>
pub fn widbus(&self) -> FieldReaderRaw<u8, u8>
Bits 14:15 - Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)
sourcepub fn negedge(&self) -> BitReaderRaw<bool>
pub fn negedge(&self) -> BitReaderRaw<bool>
Bit 16 - SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge.
sourcepub fn hwfc_en(&self) -> BitReaderRaw<bool>
pub fn hwfc_en(&self) -> BitReaderRaw<bool>
Bit 17 - Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11.
sourcepub fn ddr(&self) -> BitReaderRaw<bool>
pub fn ddr(&self) -> BitReaderRaw<bool>
Bit 18 - Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)
Methods from Deref<Target = R<CLKCR_SPEC>>
sourcepub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.