Struct stm32_hal2::pac::rcc::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 74 fields
pub cr: Reg<CR_SPEC>,
pub hsicfgr: Reg<HSICFGR_SPEC>,
pub crrcr: Reg<CRRCR_SPEC>,
pub csicfgr: Reg<CSICFGR_SPEC>,
pub cfgr: Reg<CFGR_SPEC>,
pub d1cfgr: Reg<D1CFGR_SPEC>,
pub d2cfgr: Reg<D2CFGR_SPEC>,
pub d3cfgr: Reg<D3CFGR_SPEC>,
pub pllckselr: Reg<PLLCKSELR_SPEC>,
pub pllcfgr: Reg<PLLCFGR_SPEC>,
pub pll1divr: Reg<PLL1DIVR_SPEC>,
pub pll1fracr: Reg<PLL1FRACR_SPEC>,
pub pll2divr: Reg<PLL2DIVR_SPEC>,
pub pll2fracr: Reg<PLL2FRACR_SPEC>,
pub pll3divr: Reg<PLL3DIVR_SPEC>,
pub pll3fracr: Reg<PLL3FRACR_SPEC>,
pub d1ccipr: Reg<D1CCIPR_SPEC>,
pub d2ccip1r: Reg<D2CCIP1R_SPEC>,
pub d2ccip2r: Reg<D2CCIP2R_SPEC>,
pub d3ccipr: Reg<D3CCIPR_SPEC>,
pub cier: Reg<CIER_SPEC>,
pub cifr: Reg<CIFR_SPEC>,
pub cicr: Reg<CICR_SPEC>,
pub bdcr: Reg<BDCR_SPEC>,
pub csr: Reg<CSR_SPEC>,
pub ahb3rstr: Reg<AHB3RSTR_SPEC>,
pub ahb1rstr: Reg<AHB1RSTR_SPEC>,
pub ahb2rstr: Reg<AHB2RSTR_SPEC>,
pub ahb4rstr: Reg<AHB4RSTR_SPEC>,
pub apb3rstr: Reg<APB3RSTR_SPEC>,
pub apb1lrstr: Reg<APB1LRSTR_SPEC>,
pub apb1hrstr: Reg<APB1HRSTR_SPEC>,
pub apb2rstr: Reg<APB2RSTR_SPEC>,
pub apb4rstr: Reg<APB4RSTR_SPEC>,
pub gcr: Reg<GCR_SPEC>,
pub d3amr: Reg<D3AMR_SPEC>,
pub rsr: Reg<RSR_SPEC>,
pub ahb3enr: Reg<AHB3ENR_SPEC>,
pub ahb1enr: Reg<AHB1ENR_SPEC>,
pub ahb2enr: Reg<AHB2ENR_SPEC>,
pub ahb4enr: Reg<AHB4ENR_SPEC>,
pub apb3enr: Reg<APB3ENR_SPEC>,
pub apb1lenr: Reg<APB1LENR_SPEC>,
pub apb1henr: Reg<APB1HENR_SPEC>,
pub apb2enr: Reg<APB2ENR_SPEC>,
pub apb4enr: Reg<APB4ENR_SPEC>,
pub ahb3lpenr: Reg<AHB3LPENR_SPEC>,
pub ahb1lpenr: Reg<AHB1LPENR_SPEC>,
pub ahb2lpenr: Reg<AHB2LPENR_SPEC>,
pub ahb4lpenr: Reg<AHB4LPENR_SPEC>,
pub apb3lpenr: Reg<APB3LPENR_SPEC>,
pub apb1llpenr: Reg<APB1LLPENR_SPEC>,
pub apb1hlpenr: Reg<APB1HLPENR_SPEC>,
pub apb2lpenr: Reg<APB2LPENR_SPEC>,
pub apb4lpenr: Reg<APB4LPENR_SPEC>,
pub c1_rsr: Reg<C1_RSR_SPEC>,
pub c1_ahb3enr: Reg<C1_AHB3ENR_SPEC>,
pub c1_ahb1enr: Reg<C1_AHB1ENR_SPEC>,
pub c1_ahb2enr: Reg<C1_AHB2ENR_SPEC>,
pub c1_ahb4enr: Reg<C1_AHB4ENR_SPEC>,
pub c1_apb3enr: Reg<C1_APB3ENR_SPEC>,
pub c1_apb1lenr: Reg<C1_APB1LENR_SPEC>,
pub c1_apb1henr: Reg<C1_APB1HENR_SPEC>,
pub c1_apb2enr: Reg<C1_APB2ENR_SPEC>,
pub c1_apb4enr: Reg<C1_APB4ENR_SPEC>,
pub c1_ahb3lpenr: Reg<C1_AHB3LPENR_SPEC>,
pub c1_ahb1lpenr: Reg<C1_AHB1LPENR_SPEC>,
pub c1_ahb2lpenr: Reg<C1_AHB2LPENR_SPEC>,
pub c1_ahb4lpenr: Reg<C1_AHB4LPENR_SPEC>,
pub c1_apb3lpenr: Reg<C1_APB3LPENR_SPEC>,
pub c1_apb1llpenr: Reg<C1_APB1LLPENR_SPEC>,
pub c1_apb1hlpenr: Reg<C1_APB1HLPENR_SPEC>,
pub c1_apb2lpenr: Reg<C1_APB2LPENR_SPEC>,
pub c1_apb4lpenr: Reg<C1_APB4LPENR_SPEC>,
/* private fields */
}
Expand description
Register block
Fields
cr: Reg<CR_SPEC>
0x00 - clock control register
hsicfgr: Reg<HSICFGR_SPEC>
0x04 - RCC HSI configuration register
crrcr: Reg<CRRCR_SPEC>
0x08 - RCC Clock Recovery RC Register
csicfgr: Reg<CSICFGR_SPEC>
0x0c - RCC CSI configuration register
cfgr: Reg<CFGR_SPEC>
0x10 - RCC Clock Configuration Register
d1cfgr: Reg<D1CFGR_SPEC>
0x18 - RCC Domain 1 Clock Configuration Register
d2cfgr: Reg<D2CFGR_SPEC>
0x1c - RCC Domain 2 Clock Configuration Register
d3cfgr: Reg<D3CFGR_SPEC>
0x20 - RCC Domain 3 Clock Configuration Register
pllckselr: Reg<PLLCKSELR_SPEC>
0x28 - RCC PLLs Clock Source Selection Register
pllcfgr: Reg<PLLCFGR_SPEC>
0x2c - RCC PLLs Configuration Register
pll1divr: Reg<PLL1DIVR_SPEC>
0x30 - RCC PLL1 Dividers Configuration Register
pll1fracr: Reg<PLL1FRACR_SPEC>
0x34 - RCC PLL1 Fractional Divider Register
pll2divr: Reg<PLL2DIVR_SPEC>
0x38 - RCC PLL2 Dividers Configuration Register
pll2fracr: Reg<PLL2FRACR_SPEC>
0x3c - RCC PLL2 Fractional Divider Register
pll3divr: Reg<PLL3DIVR_SPEC>
0x40 - RCC PLL3 Dividers Configuration Register
pll3fracr: Reg<PLL3FRACR_SPEC>
0x44 - RCC PLL3 Fractional Divider Register
d1ccipr: Reg<D1CCIPR_SPEC>
0x4c - RCC Domain 1 Kernel Clock Configuration Register
d2ccip1r: Reg<D2CCIP1R_SPEC>
0x50 - RCC Domain 2 Kernel Clock Configuration Register
d2ccip2r: Reg<D2CCIP2R_SPEC>
0x54 - RCC Domain 2 Kernel Clock Configuration Register
d3ccipr: Reg<D3CCIPR_SPEC>
0x58 - RCC Domain 3 Kernel Clock Configuration Register
cier: Reg<CIER_SPEC>
0x60 - RCC Clock Source Interrupt Enable Register
cifr: Reg<CIFR_SPEC>
0x64 - RCC Clock Source Interrupt Flag Register
cicr: Reg<CICR_SPEC>
0x68 - RCC Clock Source Interrupt Clear Register
bdcr: Reg<BDCR_SPEC>
0x70 - RCC Backup Domain Control Register
csr: Reg<CSR_SPEC>
0x74 - RCC Clock Control and Status Register
ahb3rstr: Reg<AHB3RSTR_SPEC>
0x7c - RCC AHB3 Reset Register
ahb1rstr: Reg<AHB1RSTR_SPEC>
0x80 - RCC AHB1 Peripheral Reset Register
ahb2rstr: Reg<AHB2RSTR_SPEC>
0x84 - RCC AHB2 Peripheral Reset Register
ahb4rstr: Reg<AHB4RSTR_SPEC>
0x88 - RCC AHB4 Peripheral Reset Register
apb3rstr: Reg<APB3RSTR_SPEC>
0x8c - RCC APB3 Peripheral Reset Register
apb1lrstr: Reg<APB1LRSTR_SPEC>
0x90 - RCC APB1 Peripheral Reset Register
apb1hrstr: Reg<APB1HRSTR_SPEC>
0x94 - RCC APB1 Peripheral Reset Register
apb2rstr: Reg<APB2RSTR_SPEC>
0x98 - RCC APB2 Peripheral Reset Register
apb4rstr: Reg<APB4RSTR_SPEC>
0x9c - RCC APB4 Peripheral Reset Register
gcr: Reg<GCR_SPEC>
0xa0 - RCC Global Control Register
d3amr: Reg<D3AMR_SPEC>
0xa8 - RCC D3 Autonomous mode Register
rsr: Reg<RSR_SPEC>
0xd0 - RCC Reset Status Register
ahb3enr: Reg<AHB3ENR_SPEC>
0xd4 - RCC AHB3 Clock Register
ahb1enr: Reg<AHB1ENR_SPEC>
0xd8 - RCC AHB1 Clock Register
ahb2enr: Reg<AHB2ENR_SPEC>
0xdc - RCC AHB2 Clock Register
ahb4enr: Reg<AHB4ENR_SPEC>
0xe0 - RCC AHB4 Clock Register
apb3enr: Reg<APB3ENR_SPEC>
0xe4 - RCC APB3 Clock Register
apb1lenr: Reg<APB1LENR_SPEC>
0xe8 - RCC APB1 Clock Register
apb1henr: Reg<APB1HENR_SPEC>
0xec - RCC APB1 Clock Register
apb2enr: Reg<APB2ENR_SPEC>
0xf0 - RCC APB2 Clock Register
apb4enr: Reg<APB4ENR_SPEC>
0xf4 - RCC APB4 Clock Register
ahb3lpenr: Reg<AHB3LPENR_SPEC>
0xfc - RCC AHB3 Sleep Clock Register
ahb1lpenr: Reg<AHB1LPENR_SPEC>
0x100 - RCC AHB1 Sleep Clock Register
ahb2lpenr: Reg<AHB2LPENR_SPEC>
0x104 - RCC AHB2 Sleep Clock Register
ahb4lpenr: Reg<AHB4LPENR_SPEC>
0x108 - RCC AHB4 Sleep Clock Register
apb3lpenr: Reg<APB3LPENR_SPEC>
0x10c - RCC APB3 Sleep Clock Register
apb1llpenr: Reg<APB1LLPENR_SPEC>
0x110 - RCC APB1 Low Sleep Clock Register
apb1hlpenr: Reg<APB1HLPENR_SPEC>
0x114 - RCC APB1 High Sleep Clock Register
apb2lpenr: Reg<APB2LPENR_SPEC>
0x118 - RCC APB2 Sleep Clock Register
apb4lpenr: Reg<APB4LPENR_SPEC>
0x11c - RCC APB4 Sleep Clock Register
c1_rsr: Reg<C1_RSR_SPEC>
0x130 - RCC Reset Status Register
c1_ahb3enr: Reg<C1_AHB3ENR_SPEC>
0x134 - RCC AHB3 Clock Register
c1_ahb1enr: Reg<C1_AHB1ENR_SPEC>
0x138 - RCC AHB1 Clock Register
c1_ahb2enr: Reg<C1_AHB2ENR_SPEC>
0x13c - RCC AHB2 Clock Register
c1_ahb4enr: Reg<C1_AHB4ENR_SPEC>
0x140 - RCC AHB4 Clock Register
c1_apb3enr: Reg<C1_APB3ENR_SPEC>
0x144 - RCC APB3 Clock Register
c1_apb1lenr: Reg<C1_APB1LENR_SPEC>
0x148 - RCC APB1 Clock Register
c1_apb1henr: Reg<C1_APB1HENR_SPEC>
0x14c - RCC APB1 Clock Register
c1_apb2enr: Reg<C1_APB2ENR_SPEC>
0x150 - RCC APB2 Clock Register
c1_apb4enr: Reg<C1_APB4ENR_SPEC>
0x154 - RCC APB4 Clock Register
c1_ahb3lpenr: Reg<C1_AHB3LPENR_SPEC>
0x15c - RCC AHB3 Sleep Clock Register
c1_ahb1lpenr: Reg<C1_AHB1LPENR_SPEC>
0x160 - RCC AHB1 Sleep Clock Register
c1_ahb2lpenr: Reg<C1_AHB2LPENR_SPEC>
0x164 - RCC AHB2 Sleep Clock Register
c1_ahb4lpenr: Reg<C1_AHB4LPENR_SPEC>
0x168 - RCC AHB4 Sleep Clock Register
c1_apb3lpenr: Reg<C1_APB3LPENR_SPEC>
0x16c - RCC APB3 Sleep Clock Register
c1_apb1llpenr: Reg<C1_APB1LLPENR_SPEC>
0x170 - RCC APB1 Low Sleep Clock Register
c1_apb1hlpenr: Reg<C1_APB1HLPENR_SPEC>
0x174 - RCC APB1 High Sleep Clock Register
c1_apb2lpenr: Reg<C1_APB2LPENR_SPEC>
0x178 - RCC APB2 Sleep Clock Register
c1_apb4lpenr: Reg<C1_APB4LPENR_SPEC>
0x17c - RCC APB4 Sleep Clock Register