Struct stm32_hal2::pac::pwr::cr3::CR3_SPEC

pub struct CR3_SPEC;

Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see cr3 module

Trait Implementations

impl Readable for CR3_SPEC

read() method returns cr3::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for CR3_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CR3_SPEC

reset() method sets CR3 to value 0x06

fn reset_value() -> <CR3_SPEC as RegisterSpec>::Ux

Reset value of the register.

impl Writable for CR3_SPEC

write(|w| ..) method takes cr3::W writer structure

type Writer = W

Writer type argument to write, et al.