pub struct W(_);Expand description
Register ISR writer
Implementations
sourceimpl W
impl W
sourcepub fn txe(&mut self) -> BitWriterRaw<'_, u32, ISR_SPEC, TXE_A, BitM, 0>
pub fn txe(&mut self) -> BitWriterRaw<'_, u32, ISR_SPEC, TXE_A, BitM, 0>
Bit 0 - Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0.
sourcepub fn txis(&mut self) -> BitWriterRaw<'_, u32, ISR_SPEC, TXIS_A, BitM, 1>
pub fn txis(&mut self) -> BitWriterRaw<'_, u32, ISR_SPEC, TXIS_A, BitM, 1>
Bit 1 - Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0.
Methods from Deref<Target = W<ISR_SPEC>>
sourcepub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.