Struct stm32_hal2::pac::i2c1::icr::W

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pub struct W(_);

Expand description

Register ICR writer

Implementations

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impl W

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pub fn addrcf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, ADDRCF_AW, BitM, 3>

Bit 3 - Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register.

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pub fn nackcf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, NACKCF_AW, BitM, 4>

Bit 4 - Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register.

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pub fn stopcf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, STOPCF_AW, BitM, 5>

Bit 5 - Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.

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pub fn berrcf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, BERRCF_AW, BitM, 8>

Bit 8 - Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.

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pub fn arlocf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, ARLOCF_AW, BitM, 9>

Bit 9 - Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.

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pub fn ovrcf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, OVRCF_AW, BitM, 10>

Bit 10 - Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register.

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pub fn peccf(&mut self) -> BitWriterRaw<'_, u32, ICR_SPEC, PECCF_AW, BitM, 11>

Bit 11 - PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.

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pub fn timoutcf(
&mut self
) -> BitWriterRaw<'_, u32, ICR_SPEC, TIMOUTCF_AW, BitM, 12>

Bit 12 - Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.

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pub fn alertcf(
&mut self
) -> BitWriterRaw<'_, u32, ICR_SPEC, ALERTCF_AW, BitM, 13>

Bit 13 - Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.

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