pub struct W(_);
Expand description
Register CR
writer
Implementations
sourceimpl W
impl W
sourcepub fn cecen(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, bool, BitM, 0>
pub fn cecen(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, bool, BitM, 0>
Bit 0 - CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.
sourcepub fn txsom(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, bool, BitM, 1>
pub fn txsom(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, bool, BitM, 1>
Bit 1 - Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception
sourcepub fn txeom(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, bool, BitM, 2>
pub fn txeom(&mut self) -> BitWriterRaw<'_, u32, CR_SPEC, bool, BitM, 2>
Bit 2 - Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message)
Methods from Deref<Target = W<CR_SPEC>>
sourcepub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.