#[repr(usize)]
pub enum DmaInput {
Show 81 variants Adc1, Adc2, Tim1Ch1, Tim1Ch2, Tim1Ch3, Tim1Ch4, Tim1Up, Tim1Trig, Tim1Com, Tim2Ch1, Tim2Ch2, Tim2Ch3, Tim2Ch4, Tim2Up, Tim3Ch1, Tim3Ch2, Tim3Ch3, Tim3Ch4, Tim3Up, Tim3Trig, Tim4Ch1, Tim4Ch2, Tim4Ch3, Tim4Up, I2c1Rx, I2c1Tx, I2c2Rx, I2c2Tx, Spi1Rx, Spi1Tx, Spi2Rx, Spi2Tx, Usart1Rx, Usart1Tx, Usart2Rx, Usart2Tx, Usart3Rx, Usart3Tx, Tim5Ch1, Tim5Ch2, Tim5Ch3, Tim5Ch4, Tim5Up, Tim5Trig, Spi3Rx, Spi3Tx, Uart4Rx, Uart4Tx, Uart5Rx, Uart5Tx, DacCh1, DacCh2, Tim6Up, Tim7Up, Uart6Rx, Uart6Tx, I2c3Rx, I2c3Tx, Dcmi, CrypIn, CrypOut, HashIn, Uart7Rx, Uart7Tx, Uart8Rx, Uart8Tx, Sai1A, Sai1B, Sai2A, Sai2B, Dfsdm1F0, Dfsdm1F1, Dfsdm1F2, Dfsdm1F3, Sai3A, Sai3B, Adc3, Uart9Rx, Uart9Tx, Uart10Rx, Uart10Tx,
}
Expand description

A list of DMA input sources. The integer values represent their DMAMUX register value, on MCUs that use this. H743 RM, Table 121: DMAMUX1: Assignment of multiplexer inputs to resources. (Table 118 in RM0468) Note that this is only for DMAMUX1

Variants

Adc1

Adc2

Tim1Ch1

Tim1Ch2

Tim1Ch3

Tim1Ch4

Tim1Up

Tim1Trig

Tim1Com

Tim2Ch1

Tim2Ch2

Tim2Ch3

Tim2Ch4

Tim2Up

Tim3Ch1

Tim3Ch2

Tim3Ch3

Tim3Ch4

Tim3Up

Tim3Trig

Tim4Ch1

Tim4Ch2

Tim4Ch3

Tim4Up

I2c1Rx

I2c1Tx

I2c2Rx

I2c2Tx

Spi1Rx

Spi1Tx

Spi2Rx

Spi2Tx

Usart1Rx

Usart1Tx

Usart2Rx

Usart2Tx

Usart3Rx

Usart3Tx

Tim5Ch1

Tim5Ch2

Tim5Ch3

Tim5Ch4

Tim5Up

Tim5Trig

Spi3Rx

Spi3Tx

Uart4Rx

Uart4Tx

Uart5Rx

Uart5Tx

DacCh1

DacCh2

Tim6Up

Tim7Up

Uart6Rx

Uart6Tx

I2c3Rx

I2c3Tx

Dcmi

CrypIn

CrypOut

HashIn

Uart7Rx

Uart7Tx

Uart8Rx

Uart8Tx

Sai1A

Sai1B

Sai2A

Sai2B

Dfsdm1F0

Dfsdm1F1

Dfsdm1F2

Dfsdm1F3

Sai3A

Sai3B

Adc3

Uart9Rx

Uart9Tx

Uart10Rx

Uart10Tx

Trait Implementations

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