Struct stm32_hal2::spi::Spi

pub struct Spi<R> {
    pub regs: R,
    pub cfg: SpiConfig,
}

Represents a Serial Peripheral Interface (SPI) peripheral.

Fields

regs: R

cfg: SpiConfig

Implementations

impl<R> Spi<R> where
    R: Deref<Target = RegisterBlock> + RccPeriph, 

pub fn new(regs: R, cfg: SpiConfig, baud_rate: BaudRate) -> Self

Initialize an SPI peripheral, including configuration register writes, and enabling and resetting its RCC peripheral clock.

pub fn reclock(&mut self, baud_rate: BaudRate)

Change the SPI baud rate.

pub fn disable(&mut self)

L44 RM, section 40.4.9: “Procedure for disabling the SPI” When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. It is important to do this before the system enters a low-power mode when the peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some modes the disable procedure is the only way to stop continuous communication running.

pub fn read(&mut self) -> Result<u8, Error>

Read a single byte if available, or block until it’s available. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn write_one(&mut self, byte: u8) -> Result<(), Error>

Write a single byte if available, or block until it’s available. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn write(&mut self, words: &[u8]) -> Result<(), Error>

Write multiple bytes on the SPI line, blocking until complete. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<(), Error>

Read multiple bytes to a buffer, blocking until complete. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub unsafe fn write_dma<D>(
    &mut self,
    buf: &[u8],
    channel: DmaChannel,
    channel_cfg: ChannelCfg,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Transmit data using DMA. See L44 RM, section 40.4.9: Communication using DMA. Note that the channel argument has no effect on F3 and L4.

pub unsafe fn read_dma<D>(
    &mut self,
    buf: &mut [u8],
    channel: DmaChannel,
    channel_cfg: ChannelCfg,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Receive data using DMA. See L44 RM, section 40.4.9: Communication using DMA. Note thay the channel argument has no effect on F3 and L4.

pub unsafe fn transfer_dma<D>(
    &mut self,
    buf_write: &[u8],
    buf_read: &mut [u8],
    channel_write: DmaChannel,
    channel_read: DmaChannel,
    channel_cfg_write: ChannelCfg,
    channel_cfg_read: ChannelCfg,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Transfer data from DMA; this is the basic reading API, using both write and read transfers: It performs a write with register data, and reads to a buffer.

Trait Implementations

impl<R> FullDuplex<u8> for Spi<R> where
    R: Deref<Target = RegisterBlock> + RccPeriph, 

type Error = Error

An enumeration of SPI errors

fn read(&mut self) -> Result<u8, Error>

Reads the word stored in the shift register

fn send(&mut self, byte: u8) -> Result<(), Error>

Sends a word to the slave

impl<R> Default<u8> for Spi<R> where
    R: Deref<Target = RegisterBlock> + RccPeriph, 

impl<R> Default<u8> for Spi<R> where
    R: Deref<Target = RegisterBlock> + RccPeriph,