Struct stm32_hal2::pac::i2c1::timingr::R

pub struct R(_);

Register TIMINGR reader

Implementations

impl R

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings.

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing.

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing.

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing.

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK

Methods from Deref<Target = R<TIMINGR_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<TIMINGR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<TIMINGR_SPEC>> for R

fn from(reader: R<TIMINGR_SPEC>) -> R

Converts to this type from the input type.