Struct stm32_hal2::timer::Timer [−][src]
pub struct Timer<TIM> {
pub regs: TIM,
// some fields omitted
}
Expand description
Represents a timer peripheral.
Fields
regs: TIM
Implementations
Configures a TIM peripheral as a periodic count down timer
Enable a specific type of ADC interrupt.
Clears interrupt associated with this timer.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.
Check if the timer is enabled.
Set the timer period, in seconds. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the timer frequency, in Hz. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the auto-reload register value. Used for adjusting frequency.
Set the prescaler value. Used for adjusting frequency.
Reset the countdown; set the counter to 0.
Configures a TIM peripheral as a periodic count down timer
Enable a specific type of ADC interrupt.
Clears interrupt associated with this timer.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.
Check if the timer is enabled.
Set the timer period, in seconds. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the timer frequency, in Hz. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the auto-reload register value. Used for adjusting frequency.
Set the prescaler value. Used for adjusting frequency.
Reset the countdown; set the counter to 0.
pub fn enable_pwm_output(
&mut self,
channel: TimChannel,
compare: OutputCompare,
dir: CountDir,
duty: f32
)
pub fn enable_pwm_output(
&mut self,
channel: TimChannel,
compare: OutputCompare,
dir: CountDir,
duty: f32
)
Enables basic PWM output
pub fn _enable_pwm_input(
&mut self,
channel: TimChannel,
compare: OutputCompare,
dir: CountDir,
duty: f32
)
pub fn _enable_pwm_input(
&mut self,
channel: TimChannel,
compare: OutputCompare,
dir: CountDir,
duty: f32
)
Enables basic PWM input. TODO: Doesn’t work yet. L4 RM, section 26.3.8
Set Output Compare Mode. See docs on the OutputCompare
enum.
Return the set duty period for a given channel. Divide by get_max_duty()
to find the portion of the duty cycle used.
Set the duty cycle, as a portion of ARR (get_max_duty()
). Note that this
needs to be re-run if you change ARR at any point.
Return the integer associated with the maximum duty period. todo: Duty could be u16 for low-precision timers.
Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Set output polarity. See docs on the Polarity
enum.
Set complementary output polarity. See docs on the Polarity
enum.
Disables capture compare on a specific channel.
Enables capture compare on a specific channel.
Set Capture Compare Mode. See docs on the CaptureCompare
enum.
Set auto reload preloader; useful when changing period and duty mid-run.
Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Setting preload is required to enable PWM.
Configures a TIM peripheral as a periodic count down timer
Enable a specific type of ADC interrupt.
Clears interrupt associated with this timer.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.
Check if the timer is enabled.
Set the timer period, in seconds. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the timer frequency, in Hz. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the auto-reload register value. Used for adjusting frequency.
Set the prescaler value. Used for adjusting frequency.
Reset the countdown; set the counter to 0.
Configures a TIM peripheral as a periodic count down timer
Enable a specific type of ADC interrupt.
Clears interrupt associated with this timer.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.
Check if the timer is enabled.
Set the timer period, in seconds. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the timer frequency, in Hz. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the auto-reload register value. Used for adjusting frequency.
Set the prescaler value. Used for adjusting frequency.
Reset the countdown; set the counter to 0.
Configures a TIM peripheral as a periodic count down timer
Enable a specific type of ADC interrupt.
Clears interrupt associated with this timer.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.
Check if the timer is enabled.
Set the timer period, in seconds. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the timer frequency, in Hz. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the auto-reload register value. Used for adjusting frequency.
Set the prescaler value. Used for adjusting frequency.
Reset the countdown; set the counter to 0.
Configures a TIM peripheral as a periodic count down timer
Enable a specific type of ADC interrupt.
Clears interrupt associated with this timer.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished. For examlpe, place this at the top of your timer’s interrupt handler.
Check if the timer is enabled.
Set the timer period, in seconds. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the timer frequency, in Hz. Overrides the period or frequency set
in the constructor. If you use center
aligned PWM, make sure to
enter twice the freq you normally would.
Set the auto-reload register value. Used for adjusting frequency.
Set the prescaler value. Used for adjusting frequency.
Reset the countdown; set the counter to 0.