Struct stm32_hal2::sai::SaiConfig [−][src]
pub struct SaiConfig {Show 14 fields
pub mode: SaiMode,
pub protocol: Protocol,
pub mono: Mono,
pub sync: SyncMode,
pub datasize: DataSize,
pub master_clock: MasterClock,
pub first_bit: FirstBit,
pub oversampling_ratio: OversamplingRatio,
pub frame_length: u16,
pub fs_offset: FsOffset,
pub fs_polarity: FsPolarity,
pub fs_signal: FsSignal,
pub num_slots: u8,
pub fifo_thresh: FifoThresh,
}
Expand description
Configuration for the SAI peripheral. Mainly affects the ACR and BCR registers. Used for either channel. For details, see documentation of individual structs and fields. You may be forced into certain settings based on the device used.
Fields
mode: SaiMode
protocol: Protocol
mono: Mono
sync: SyncMode
An audio subblock can be configured to operate synchronously with the second audio subblock in the same SAI. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication.
datasize: DataSize
master_clock: MasterClock
first_bit: FirstBit
oversampling_ratio: OversamplingRatio
frame_length: u16
Eefine the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NOMCK = 1), it is recommended to program the frame length to an value ranging from 8 to 256.
fs_offset: FsOffset
fs_polarity: FsPolarity
fs_signal: FsSignal
num_slots: u8
fifo_thresh: FifoThresh
The FIFO threshold configures when the FREQ interrupt is generated based on how full the FIFO is.
Implementations
Default configuration for I2S.
Default configuration for PDM
Default configuration for AC’97
Default configuration for SPDIF