Struct stm32_hal2::sai::Sai

pub struct Sai<R> {
    pub config_a: SaiConfig,
    pub config_b: SaiConfig,
    // some fields omitted
}

Represents the USART peripheral, for serial communications.

Fields

config_a: SaiConfig

config_b: SaiConfig

Implementations

impl<R> Sai<R> where
    R: Deref<Target = RegisterBlock>, 

pub fn new(
    regs: R,
    device: SaiDevice,
    config_a: SaiConfig,
    config_b: SaiConfig,
    clocks: &Clocks
) -> Self

pub fn enable(&mut self, channel: SaiChannel)

Enable an audio subblock (channel).

pub fn disable(&mut self, channel: SaiChannel)

Disable an audio subblock (channel). See H743 RM, section 51.4.15. The SAI audio block can be disabled at any moment by clearing SAIEN bit in the SAI_xCR1 register. All the already started frames are automatically completed before the SAI is stops working. SAIEN bit remains High until the SAI is completely switched-off at the end of the current audio frame transfer. If an audio block in the SAI operates synchronously with the other one, the one which is the master must be disabled first.

pub fn read(&self, channel: SaiChannel) -> (u32, u32)

Read 2 words of data from a channel. A read from the SR register empties the FIFO if the FIFO is not empty

pub fn write(&mut self, channel: SaiChannel, left_word: u32, right_word: u32)

Send 2 words of data to a single channel. A write to the SR register loads the FIFO provided the FIFO is not full.

pub unsafe fn write_dma<D>(
    &mut self,
    buf: &[u32],
    sai_channel: SaiChannel,
    dma_channel: DmaChannel,
    channel_cfg: ChannelCfg,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Send data over SAI with DMA. H743 RM, section 51.4.16: SAI DMA Interface. To free the CPU and to optimize bus bandwidth, each SAI audio block has an independent DMA interface to read/write from/to the SAI_xDR register (to access the internal FIFO). There is one DMA channel per audio subblock supporting basic DMA request/acknowledge protocol.

pub unsafe fn read_dma<D>(
    &mut self,
    buf: &mut [u32],
    sai_channel: SaiChannel,
    dma_channel: DmaChannel,
    channel_cfg: ChannelCfg,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Read data from SAI with DMA. H743 RM, section 51.4.16: SAI DMA Interface. To free the CPU and to optimize bus bandwidth, each SAI audio block has an independent DMA interface to read/write from/to the SAI_xDR register (to access the internal FIFO). There is one DMA channel per audio subblock supporting basic DMA request/acknowledge protocol.

pub fn enable_interrupt(
    &mut self,
    interrupt_type: SaiInterrupt,
    channel: SaiChannel
)

Enable a specific type of interrupt. See L4 RM, Table 220: “SAI interrupt sources”.

pub fn clear_interrupt(
    &mut self,
    interrupt_type: SaiInterrupt,
    channel: SaiChannel
)

Clears the interrupt pending flag for a specific type of interrupt.