Struct stm32_hal2::clocks::Clocks

pub struct Clocks {

    pub input_src: InputSrc,
    pub pllm: Pllm,
    pub plln: u8,
    pub pll_sai1_mul: u8,
    pub pll_sai2_mul: u8,
    pub pllr: Pllr,
    pub pllq: Pllr,
    pub hclk_prescaler: HclkPrescaler,
    pub apb1_prescaler: ApbPrescaler,
    pub apb2_prescaler: ApbPrescaler,
    pub clk48_src: Clk48Src,
    pub sai1_enabled: bool,
    pub sai2_enabled: bool,
    pub hse_bypass: bool,
    pub security_system: bool,
    pub hsi48_on: bool,
    pub stop_wuck: StopWuck,
}

Settings used to configure clocks.

Fields

input_src: InputSrc

The input source for the system and peripheral clocks. Eg HSE, HSI, PLL etc

pllm: Pllm

plln: u8

pll_sai1_mul: u8

pll_sai2_mul: u8

pllr: Pllr

pllq: Pllr

hclk_prescaler: HclkPrescaler

The value to divide SYSCLK by, to get systick and peripheral clocks. Also known as AHB divider

apb1_prescaler: ApbPrescaler

The divider of HCLK to get the APB1 peripheral clock

apb2_prescaler: ApbPrescaler

The divider of HCLK to get the APB2 peripheral clock

clk48_src: Clk48Src

The input source for the 48Mhz clock used by USB.

sai1_enabled: bool

sai2_enabled: bool

hse_bypass: bool

Bypass the HSE output, for use with oscillators that don’t need it. Saves power, and frees up the pin for use as GPIO.

security_system: bool

hsi48_on: bool

Enable the HSI48. For L4, this is only applicable on L49X and L4Ax devices.

stop_wuck: StopWuck

Select the input source to use after waking up from stop mode. Eg HSI or MSI.

Implementations

impl Clocks

pub fn setup(&self, rcc: &mut RCC, flash: &mut FLASH) -> Result<(), SpeedError>

Setup common and return a Valid status if the config is valid. Return Invalid, and don’t setup if not. https://docs.rs/stm32f3xx-hal/0.5.0/stm32f3xx_hal/rcc/struct.CFGR.html Use the STM32CubeIDE Clock Configuration tab to help.

pub fn reselect_input(&self, rcc: &mut RCC)

Re-select input source; used after Stop and Standby modes, where the system reverts to MSI or HSI after wake.

pub fn change_msi_speed(&mut self, range: MsiRange, rcc: &mut RCC)

Use this to change the MSI speed. Run this only if your clock source is MSI. Ends in a state with MSI on at the new speed, and HSI off.

pub fn enable_msi_48(&self, rcc: &mut RCC)

Enables MSI, and configures it at 48Mhz, and trims it using the LSE. This is useful when using it as the USB clock, ie with clk48_src: Clk48Src::Msi. Don’t use this if using MSI for the input source or PLL source. You may need to re-run this after exiting stop mode. Only works for USB if you have an LSE connected. Note: MSIPLLEN must be enabled after LSE is enabled. So, run this function after RCC clock setup.

pub fn pll_is_enabled(&self, rcc: &mut RCC) -> bool

Check if the PLL is enabled. This is useful if checking wheather to re-enable the PLL after exiting Stop or Standby modes, eg so you don’t re-enable if it was already re-enabled in a different context. eg:

if !clock_cfg.pll_is_enabled() {
    clock_cfg.reselect_input(&mut dp.RCC);
}

Trait Implementations

impl ClockCfg for Clocks

fn sysclk(&self) -> u32

System clock speed, in Hz.

fn hclk(&self) -> u32

HCLK speed, in Hz. Ie AHB bus, core, memory, and DMA.

fn systick(&self) -> u32

Cortex System timer speed, in Hz.

fn usb(&self) -> u32

USB speed, in Hz.

fn apb1(&self) -> u32

APB1 peripheral common speed, in Hz.

fn apb1_timer(&self) -> u32

APB1 timer common speed, in Hz.

fn apb2(&self) -> u32

APB2 timer common speed, in Hz.

fn apb2_timer(&self) -> u32

APB2 peripheral common speed, in Hz.

fn validate_speeds(&self) -> ClocksValid

Validate that the clocks speeds are all within the acceptable range for the MCU // todo Separate USB validation? back to Validation enum, or keep it simple?

impl Default for Clocks

fn default() -> Self

This default configures common with a HSI, a 80Mhz sysclck (l4). All peripheral clocks are at 80Mhz (l4). L5 speeds: 108Mhz. G4 speeds: 168Mhz.