Struct stm32_hal2::clocks::Clocks

pub struct Clocks {
    pub input_src: InputSrc,
    pub pllm: Pllm,
    pub pll_vco_mul: u8,
    pub pll_sai1_mul: u8,
    pub pll_sai2_mul: u8,
    pub pllr: Pllr,
    pub hclk_prescaler: HclkPrescaler,
    pub apb1_prescaler: ApbPrescaler,
    pub apb2_prescaler: ApbPrescaler,
    pub clk48_src: Clk48Src,
    pub sai1_enabled: bool,
    pub sai2_enabled: bool,
    pub hse_bypass: bool,
    pub security_system: bool,
}

Settings used to configure clocks.

Fields

input_src: InputSrc

pllm: Pllm

pll_vco_mul: u8

pll_sai1_mul: u8

pll_sai2_mul: u8

pllr: Pllr

hclk_prescaler: HclkPrescaler

apb1_prescaler: ApbPrescaler

apb2_prescaler: ApbPrescaler

clk48_src: Clk48Src

sai1_enabled: bool

sai2_enabled: bool

hse_bypass: bool

security_system: bool

Implementations

impl Clocks

pub fn setup(&self, rcc: &mut RCC, flash: &mut FLASH) -> Result<(), SpeedError>

Setup common and return a Valid status if the config is valid. Return Invalid, and don’t setup if not. https://docs.rs/stm32f3xx-hal/0.5.0/stm32f3xx_hal/rcc/struct.CFGR.html Use the STM32CubeIDE Clock Configuration tab to help.

pub fn hsi_preset() -> Self

This preset configures common with a HSI, a 80Mhz sysclck. All peripheral common are at 80Mhz. HSE output is not bypassed.

Trait Implementations

impl ClockCfg for Clocks

fn sysclk(&self) -> u32

System clock speed, in Hz.

fn hclk(&self) -> u32

HCLK speed, in Hz. Ie AHB bus, core, memory, and DMA.

fn systick(&self) -> u32

Cortex System timer speed, in Hz.

fn usb(&self) -> u32

USB speed, in Hz.

fn apb1(&self) -> u32

APB1 peripheral common speed, in Hz.

fn apb1_timer(&self) -> u32

APB1 timer common speed, in Hz.

fn apb2(&self) -> u32

APB2 timer common speed, in Hz.

fn apb2_timer(&self) -> u32

APB2 peripheral common speed, in Hz.

fn validate_speeds(&self) -> ClocksValid

Validate that the clocks speeds are all within the acceptable range for the MCU // todo Separate USB validation? back to Validation enum, or keep it simple?

impl Default for Clocks

fn default() -> Self

This default configures common with a HSE, a 32Mhz sysclck. All peripheral common are at 32 Mhz. HSE output is not bypassed.