pub fn new<'rx, 'tx, REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1>(
parts: PartsIn,
rx_buffer: &'rx mut [RxRingEntry],
tx_buffer: &'tx mut [TxRingEntry],
clocks: Clocks,
pins: EthPins<REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1>,
) -> Result<Parts<'rx, 'tx, EthernetMAC>, WrongClock>where
REFCLK: RmiiRefClk + AlternateVeryHighSpeed,
CRS: RmiiCrsDv + AlternateVeryHighSpeed,
TXEN: RmiiTxEN + AlternateVeryHighSpeed,
TXD0: RmiiTxD0 + AlternateVeryHighSpeed,
TXD1: RmiiTxD1 + AlternateVeryHighSpeed,
RXD0: RmiiRxD0 + AlternateVeryHighSpeed,
RXD1: RmiiRxD1 + AlternateVeryHighSpeed,
Expand description
Create and initialise the ethernet driver.
Initialize and start tx and rx DMA engines. Sets up the peripheral clocks and GPIO configuration, and configures the ETH MAC and DMA peripherals. Automatically sets slew rate to VeryHigh.
The speed of the MAC is set to Speed::FullDuplexBase100Tx
.
This can be changed using EthernetMAC::set_speed
.
This method does not initialise the external PHY. Interacting with a PHY
can be done by using the struct returned from EthernetMAC::mii
.
ยงNote
- Make sure that the buffers reside in a memory region that is accessible by the peripheral. Core-Coupled Memory (CCM) is usually not accessible.
- HCLK must be at least 25 MHz.