Struct stm32_eth::stm32::rcc::ahb1enr::W

pub struct W(/* private fields */);

Register AHB1ENR writer

Implementations

impl W

pub fn otghsulpien( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 30>

Bit 30 - USB OTG HSULPI clock enable

pub fn otghsen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 29>

Bit 29 - USB OTG HS clock enable

pub fn ethmacptpen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 28>

Bit 28 - Ethernet PTP clock enable

pub fn ethmacrxen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 27>

Bit 27 - Ethernet Reception clock enable

pub fn ethmactxen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 26>

Bit 26 - Ethernet Transmission clock enable

pub fn ethmacen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 25>

Bit 25 - Ethernet MAC clock enable

pub fn dma2en( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 22>

Bit 22 - DMA2 clock enable

pub fn dma1en( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 21>

Bit 21 - DMA1 clock enable

pub fn ccmdataramen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 20>

Bit 20 - CCM data RAM clock enable

pub fn bkpsramen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 18>

Bit 18 - Backup SRAM interface clock enable

pub fn crcen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 12>

Bit 12 - CRC clock enable

pub fn gpioien( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 8>

Bit 8 - IO port I clock enable

pub fn gpiohen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 7>

Bit 7 - IO port H clock enable

pub fn gpiogen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 6>

Bit 6 - IO port G clock enable

pub fn gpiofen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 5>

Bit 5 - IO port F clock enable

pub fn gpioeen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 4>

Bit 4 - IO port E clock enable

pub fn gpioden( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 3>

Bit 3 - IO port D clock enable

pub fn gpiocen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 2>

Bit 2 - IO port C clock enable

pub fn gpioben( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 1>

Bit 1 - IO port B clock enable

pub fn gpioaen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 0>

Bit 0 - IO port A clock enable

pub fn dma2den( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 23>

Bit 23 - DMA2D clock enable

pub fn gpiojen( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 9>

Bit 9 - IO port J clock enable

pub fn gpioken( &mut self ) -> BitWriterRaw<'_, u32, AHB1ENR_SPEC, GPIOAEN_A, BitM, 10>

Bit 10 - IO port K clock enable

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<AHB1ENR_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<AHB1ENR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<AHB1ENR_SPEC>> for W

fn from(writer: W<AHB1ENR_SPEC>) -> W

Converts to this type from the input type.