Enum Regs 

#[non_exhaustive]
pub enum Regs {
    X86_64 {
        rip: u64,
        rsp: u64,
        gprs: [u64; 16],
    },
    Aarch64 {
        pc: u64,
        sp_el1: u64,
        gprs: [u64; 31],
        pstate: u64,
    },
}

Architecture-tagged register file.

Different backends own different register subsets — a KVM x86 vCPU exposes CR0/CR3/EFER/MSRs that don’t exist on aarch64 HVF, and vice versa. We model that with a sum type and let each backend convert to/from its native struct in its own crate.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

X86_64

x86_64 register file. Field set is intentionally minimal in squib-core; backend crates carry richer typed structs for their own use.

Fields

rip: u64

Instruction pointer.

rsp: u64

Stack pointer.

gprs: [u64; 16]

16 general-purpose registers in the canonical order (RAX, RBX, RCX, RDX, RSI, RDI, RBP, R8, R9, R10, R11, R12, R13, R14, R15, FLAGS).

Aarch64

aarch64 register file (EL1). PC + 31 GPRs (X0..X30) + SP_EL1 + PSTATE.

Fields

pc: u64

Program counter.

sp_el1: u64

Stack pointer at EL1.

gprs: [u64; 31]

31 general-purpose registers (X0..X30).

pstate: u64

Processor state register.

Trait Implementations

impl Clone for Regs

fn clone(&self) -> Regs

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Regs

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.