Enum Operator 

pub enum Operator {
    Add,
    UnsignedAdd,
    Sub,
    UnsignedSub,
    Mul,
    UnsignedMul,
    Div,
    UnsignedDiv,
    Mod,
    UnsignedMod,
    Eq,
    NotEq,
    Gt,
    UnsignedGt,
    Lt,
    UnsignedLt,
    Ge,
    UnsignedGe,
    Le,
    UnsignedLe,
    LeftShift,
    RightShift,
    ArithmeticRightShift,
    LogicalAnd,
    LogicalOr,
    LogicalXor,
    LogicalNot,
    BitwiseAnd,
    BitwiseOr,
    BitwiseXor,
    ReduceAnd,
    ReduceOr,
    ReduceXor,
    USub,
    Not,
    ReadPort,
    BitwiseNot,
    DivPow2,
    SignExtend {
        extra_bits: BigUint,
        operand_size: BigUint,
    },
    ZeroExtend {
        extra_bits: BigUint,
    },
    Truncate,
    Concat,
    Select,
    Match,
    ConstructArray,
    DeclClockedMemory {
        write_ports: BigUint,
        addr_w: BigUint,
        inner_w: BigUint,
        elems: BigUint,
        initial: Option<Vec<Vec<Statement>>>,
    },
    IndexArray {
        array_size: BigUint,
    },
    IndexMemory,
    RangeIndexArray {
        start: BigUint,
        end_exclusive: BigUint,
        in_array_size: BigUint,
    },
    RangeIndexBits {
        start: BigUint,
        end_exclusive: BigUint,
    },
    ConstructTuple,
    ConstructEnum {
        variant: usize,
        variant_count: usize,
    },
    IsEnumVariant {
        variant: usize,
        enum_type: Type,
    },
    EnumMember {
        enum_type: Type,
        variant: usize,
        member_index: usize,
    },
    IndexTuple(u64, Vec<Type>),
    FlipPort,
    ReadMutWires,
    Instance {
        name: UnitName,
        params: Vec<(String, BigUint)>,
        argument_names: Vec<ParamName>,
        loc: Option<Loc<()>>,
    },
    Alias,
    Nop,
}

Variants

Add

UnsignedAdd

Sub

UnsignedSub

Mul

UnsignedMul

Div

UnsignedDiv

Mod

UnsignedMod

Eq

NotEq

Gt

UnsignedGt

Lt

UnsignedLt

Ge

UnsignedGe

Le

UnsignedLe

LeftShift

RightShift

ArithmeticRightShift

LogicalAnd

LogicalOr

LogicalXor

LogicalNot

BitwiseAnd

BitwiseOr

BitwiseXor

ReduceAnd

ReduceOr

ReduceXor

USub

Not

ReadPort

BitwiseNot

DivPow2

SignExtend

Sign extend the first operand with the provided amount of extra bits

Fields

extra_bits: BigUint

operand_size: BigUint

ZeroExtend

Fields

extra_bits: BigUint

Truncate

Truncate the first operand to fit the size of the target operand. Should not be used on operands which are smaller than the target

Concat

Concatenate the bits of all input operands

Select

Select [1] if [0] else [2]

Match

Corresponds to a match statement. If value [0] is true, select [1], if [2] holds, select [3] and so on. Values are priorotized in order, i.e. if both [0] and [2] hold, [1] is selected

ConstructArray

Construct an array from the operand expressions

DeclClockedMemory

Create a mutable array which is modified on the rising edge of the first argument. the second argument is an array of (write enable, write address, write data) tuples which update the array.

Fields

write_ports: BigUint

addr_w: BigUint

Width of the write address

inner_w: BigUint

Number of elements in the array

elems: BigUint

Number of elements in the array

initial: Option<Vec<Vec<Statement>>>

Initial values for the memory. Must be const evaluatable

IndexArray

Index an array with elements of the specified size

Fields

array_size: BigUint

IndexMemory

RangeIndexArray

Indexes an array to extract a range of elements

Fields

start: BigUint

end_exclusive: BigUint

in_array_size: BigUint

RangeIndexBits

Compiles to verilog [end_exclusive:start]. Supports single bit indexing, (when end_exclusive == start + 1, in which case it compiles to [start]

Fields

start: BigUint

end_exclusive: BigUint

ConstructTuple

Construct a tuple from all the operand expressions

ConstructEnum

Construct the nth enum variant with the operand expressions as the payload

Fields

variant: usize

variant_count: usize

IsEnumVariant

1 if the input is the specified enum variant

Fields

variant: usize

enum_type: Type

EnumMember

Get the member_indexth member of the variantth variant.

Fields

enum_type: Type

variant: usize

member_index: usize

IndexTuple(u64, Vec<Type>)

Get the .0th element of a tuple or a type of the same representation as a tuple, for example a Struct. The types of the elements are specified in the second argument

FlipPort

Inverts the direction of all bits of a port. I.e. the forward ports become backward ports. This is only valid when converting from T to ~T

ReadMutWires

Given a struct or tuple consisting of mut and non-mut wires, create a new struct or tuple with the non-mut copies of the mut wires

As an example (&mut T1, T2, &mut T3) becomes (T1, T3)

Instance

Instantiation of another module with the specified name. The operands are passed by name to the entity. The operand name mapping is decided by the argument_names field of this variant. The first operand gets mapped to the first argument name, and so on. The target module can only have a single output which must be the last argument. The location of the instantiation is optional but can be passed to improve critical path report readability

Fields

name: UnitName

params: Vec<(String, BigUint)>

argument_names: Vec<ParamName>

The names of the arguments in the same order as the operands. For instance, if the ith argument name is “foo” and the ith Binding is my_port, the verilog module will be instantiated with .foo(my_port).

loc: Option<Loc<()>>

Alias

Alias another named value

Nop

Define a variable for the value but don’t do anything with it. Useful for creating ports

Implementations

impl Operator

pub fn simple_instance(name: UnitName, argument_names: Vec<&str>) -> Self

Trait Implementations

impl Clone for Operator

fn clone(&self) -> Operator

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Operator

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for Operator

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for Operator

fn hash<__H: Hasher>(&self, __state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for Operator

fn eq(&self, __other: &Self) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for Operator