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ComputeInstructions

sp1_jit::instructions

Trait ComputeInstructions 

Source 
pub trait ComputeInstructions: Sized {

Show 30 methods    // Required methods
    fn add(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn sub(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn xor(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn or(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn and(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn sll(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn srl(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn sra(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn slt(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn sltu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn mul(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn mulh(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn mulhu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn mulhsu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn div(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn divu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn rem(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn remu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn addw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn subw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn sllw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn srlw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn sraw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn mulw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn divw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn divuw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn remw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn remuw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand);
    fn auipc(&mut self, rd: RiscRegister, imm: u64);
    fn lui(&mut self, rd: RiscRegister, imm: u64);

}
Expand description

An ALU instruction backend for a specific target architecture.

This trait is implemented for each target architecture supported by the JIT transpiler.

Required Methods§

Source

fn add(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Add the values of two registers together, using 64bit arithmetic.

add: rd = rs1 + rs2

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fn sub(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Subtract the values of two registers from each other, using 64bit arithmetic.

sub: rd = rs1 - rs2

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fn xor(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Bitwise XOR the values of two registers together.

xor: rd = rs1 ^ rs2

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fn or(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Bitwise OR the values of two registers together.

or: rd = rs1 | rs2

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fn and(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Bitwise AND the values of two registers together.

and: rd = rs1 & rs2

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fn sll(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Shift the values of two registers left by the amount specified by the second register.

sll: rd = rs1 << rs2

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fn srl(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Shift the values of two registers right by the amount specified by the second register.

srl: rd = rs1 >> rs2

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fn sra(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Shift the values of two registers right by the amount specified by the second register, using arithmetic right shift.

sra: rd = rs1 >> rs2

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fn slt(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Set if less than (signed comparison).

slt: rd = (rs1 < rs2) ? 1 : 0

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fn sltu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Set if less than (unsigned comparison).

sltu: rd = (rs1 < rs2) ? 1 : 0

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fn mul(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Multiply the values of two registers together, using 64bit arithmetic.

mul: rd = rs1 * rs2

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fn mulh(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Multiply the values of two registers together and return the high 64 bits (signed).

mulh: rd = (rs1 * rs2) >> 64 (signed)

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fn mulhu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Multiply the values of two registers together and return the high 64 bits (unsigned).

mulhu: rd = (rs1 * rs2) >> 64 (unsigned)

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fn mulhsu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Multiply signed rs1 by unsigned rs2 and return the high 64 bits.

mulhsu: rd = (rs1 * rs2) >> 64 (signed * unsigned)

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fn div(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Divide the values of two registers (signed).

div: rd = rs2 == 0 ? 0 : rs1 / rs2

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fn divu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Divide the values of two registers (unsigned).

divu: rd = rs2 == 0 ? 0 : rs1 / rs2

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fn rem(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Remainder of two registers (signed).

rem: rd = rs2 == 0 ? 0 : rs1 % rs2

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fn remu(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Remainder of two registers (unsigned).

remu: rd = rs2 == 0 ? 0 : rs1 % rs2

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fn addw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Add the values of two registers together, using 64bit arithmetic, but only keeping lower 32 bits.

addw: rd = (rs1 + rs2) & 0xFFFFFFFF (sign-extended to 64-bit)

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fn subw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Subtract the values of two registers, using 64bit arithmetic, but only keeping lower 32 bits.

subw: rd = (rs1 - rs2) & 0xFFFFFFFF (sign-extended to 64-bit)

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fn sllw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Shift the values of two registers left by the amount specified by the second register (32-bit).

sllw: rd = (rs1 << (rs2 & 0x1F)) & 0xFFFFFFFF (sign-extended to 64-bit)

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fn srlw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Shift the values of two registers right by the amount specified by the second register (32-bit logical).

srlw: rd = ((rs1 & 0xFFFFFFFF) >> (rs2 & 0x1F)) (sign-extended to 64-bit)

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fn sraw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Shift the values of two registers right by the amount specified by the second register (32-bit arithmetic).

sraw: rd = ((rs1 as i32) >> (rs2 & 0x1F)) (sign-extended to 64-bit)

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fn mulw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Multiply the values of two registers together, using 32bit arithmetic (sign-extended to 64-bit).

mulw: rd = (rs1 * rs2) & 0xFFFFFFFF (sign-extended to 64-bit)

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fn divw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Divide the values of two registers together, using 32bit arithmetic (sign-extended to 64-bit).

divw: rd = rs2 == 0 ? 0xFFFFFFFF : (rs1 as i32) / (rs2 as i32) (sign-extended to 64-bit)

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fn divuw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Divide the values of two registers, unsigned 32bit (sign-extended to 64-bit).

divuw: rd = rs2 == 0 ? 0xFFFFFFFF : (rs1 as u32) / (rs2 as u32) (sign-extended to 64-bit)

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fn remw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Remainder the values of two registers together, using 32bit arithmetic (sign-extended to 64-bit).

remw: rd = rs2 == 0 ? rs1 : (rs1 as i32) % (rs2 as i32) (sign-extended to 64-bit)

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fn remuw(&mut self, rd: RiscRegister, rs1: RiscOperand, rs2: RiscOperand)

Remainder the values of two registers, unsigned 32bit (sign-extended to 64-bit).

remuw: rd = rs2 == 0 ? rs1 : (rs1 as u32) % (rs2 as u32) (sign-extended to 64-bit)

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fn auipc(&mut self, rd: RiscRegister, imm: u64)

Advance to the next pc, storing the current (pc + imm) in a register.

auipc: rd = pc + imm, pc = pc + 4

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fn lui(&mut self, rd: RiscRegister, imm: u64)

Load upper immediate into a register.

lui: rd = imm << 12

Dyn Compatibility§

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementors§