sp1_core_machine/memory/consistency/
columns.rs

1use serde::{Deserialize, Serialize};
2use sp1_derive::{AlignedBorrow, IntoShape};
3use sp1_hypercube::Word;
4
5use crate::operations::U16toU8Operation;
6
7/// Memory Access Timestamp
8#[derive(AlignedBorrow, Default, Debug, Clone, Copy)]
9#[repr(C)]
10pub struct MemoryAccessTimestamp<T> {
11    /// The previous timestamp's high 24 bits that this memory access is being read from.
12    pub prev_high: T,
13    /// The previous timestamp's low 24 bits that this memory access is being read from.
14    pub prev_low: T,
15    /// This will be true if the top 24 bits do not match.
16    pub compare_low: T,
17    /// The following columns are decomposed limbs for the difference between the current access's
18    /// timestamp and the previous access's timestamp.  Note the actual value of the timestamp
19    /// is either the accesses' high or low 24 bits depending on the value of compare_low.
20    ///
21    /// This column is the least significant 16 bit limb of the difference.
22    pub diff_low_limb: T,
23    /// This column is the most significant 8 bit limb of the difference.
24    pub diff_high_limb: T,
25}
26
27/// Memory Access Columns
28#[derive(AlignedBorrow, Default, Debug, Clone, Copy)]
29#[repr(C)]
30pub struct MemoryAccessCols<T> {
31    pub prev_value: Word<T>,
32    pub access_timestamp: MemoryAccessTimestamp<T>,
33}
34
35/// Memory Access Columns for u8 limbs
36#[derive(AlignedBorrow, Default, Debug, Clone, Copy)]
37#[repr(C)]
38pub struct MemoryAccessColsU8<T> {
39    pub memory_access: MemoryAccessCols<T>,
40    pub prev_value_u8: U16toU8Operation<T>,
41}
42
43/// Register Access Timestamp. The register accesses use the same argument as the memory accesses,
44/// and shares the same space as the memory. This structure is used for register accesses in RISC-V.
45/// For optimization, we ensure that all register accesses have the high limb of the timestamp and
46/// previous timestamp to be equal. This is done through adding in a "shadow" read, through the
47/// `MemoryBump` chip. Therefore, only the columns for low limb comparison is needed here.
48#[derive(AlignedBorrow, Default, Debug, Clone, Copy, Serialize, Deserialize, IntoShape)]
49#[repr(C)]
50pub struct RegisterAccessTimestamp<T> {
51    /// The previous timestamp that this memory access is being read from.
52    pub prev_low: T,
53    /// The difference in timestamp's least significant 16 bit limb.
54    pub diff_low_limb: T,
55}
56
57/// Register Access Columns
58#[derive(AlignedBorrow, Default, Debug, Clone, Copy, Serialize, Deserialize, IntoShape)]
59#[repr(C)]
60pub struct RegisterAccessCols<T> {
61    pub prev_value: Word<T>,
62    pub access_timestamp: RegisterAccessTimestamp<T>,
63}
64
65/// Page Permission Access Columns, when the shard and previous shard are known to be equal
66#[derive(AlignedBorrow, Default, Debug, Clone, Copy)]
67#[repr(C)]
68pub struct PageProtAccessCols<T> {
69    pub prev_prot_bitmap: T,
70    pub access_timestamp: MemoryAccessTimestamp<T>,
71}
sp1_core_machine/memory/consistency/columns.rs

sp1_core_machine/memory/consistency/
columns.rs
