Struct CpuCols

#[repr(C)]
pub struct CpuCols<T: Copy> {

    pub shard: T,
    pub nonce: T,
    pub clk: T,
    pub clk_16bit_limb: T,
    pub clk_8bit_limb: T,
    pub pc: T,
    pub next_pc: T,
    pub instruction: InstructionCols<T>,
    pub selectors: OpcodeSelectorCols<T>,
    pub op_a_access: MemoryReadWriteCols<T>,
    pub op_b_access: MemoryReadCols<T>,
    pub op_c_access: MemoryReadCols<T>,
    pub opcode_specific_columns: OpcodeSpecificCols<T>,
    pub is_real: T,
    pub branching: T,
    pub not_branching: T,
    pub mem_value_is_neg_not_x0: T,
    pub mem_value_is_pos_not_x0: T,
    pub unsigned_mem_val: Word<T>,
    pub unsigned_mem_val_nonce: T,
    pub ecall_mul_send_to_table: T,
    pub ecall_range_check_operand: T,
    pub is_sequential_instr: T,
}

The column layout for the CPU.

Fields

shard: T

The current shard.

nonce: T

clk: T

The clock cycle value. This should be within 24 bits.

clk_16bit_limb: T

The least significant 16 bit limb of clk.

clk_8bit_limb: T

The most significant 8 bit limb of clk.

pc: T

The program counter value.

next_pc: T

The expected next program counter value.

instruction: InstructionCols<T>

Columns related to the instruction.

selectors: OpcodeSelectorCols<T>

Selectors for the opcode.

op_a_access: MemoryReadWriteCols<T>

Operand values, either from registers or immediate values.

op_b_access: MemoryReadCols<T>

op_c_access: MemoryReadCols<T>

opcode_specific_columns: OpcodeSpecificCols<T>

is_real: T

Selector to label whether this row is a non padded row.

branching: T

The branching column is equal to:

is_beq & a_eq_b || is_bne & (a_lt_b | a_gt_b) || (is_blt | is_bltu) & a_lt_b || (is_bge | is_bgeu) & (a_eq_b | a_gt_b)

not_branching: T

The not branching column is equal to:

is_beq & !a_eq_b || is_bne & !(a_lt_b | a_gt_b) || (is_blt | is_bltu) & !a_lt_b || (is_bge | is_bgeu) & !(a_eq_b | a_gt_b)

mem_value_is_neg_not_x0: T

Flag for load mem instructions where the value is negative and not writing to x0. More formally, it is

(is_lb | is_lh) & (most_sig_byte_decomp[7] == 1) & (not writing to x0)

mem_value_is_pos_not_x0: T

Flag for load mem instructions where the value is positive and not writing to x0. More formally, it is

( ((is_lb | is_lh) & (most_sig_byte_decomp[7] == 0)) | is_lbu | is_lhu | is_lw ) & (not writing to x0)

unsigned_mem_val: Word<T>

The unsigned memory value is the value after the offset logic is applied. Used for the load memory opcodes (i.e. LB, LH, LW, LBU, and LHU).

unsigned_mem_val_nonce: T

ecall_mul_send_to_table: T

The result of selectors.is_ecall * the send_to_table column for the ECALL opcode.

ecall_range_check_operand: T

The result of selectors.is_ecall * (is_halt || is_commit_deferred_proofs)

is_sequential_instr: T

This is true for all instructions that are not jumps, branches, and halt. Those instructions may move the program counter to a non sequential instruction.

Implementations

impl<T: Copy> CpuCols<T>

pub fn op_a_val(&self) -> Word<T>

Gets the value of the first operand.

pub fn op_b_val(&self) -> Word<T>

Gets the value of the second operand.

pub fn op_c_val(&self) -> Word<T>

Gets the value of the third operand.

Trait Implementations

impl<T: Copy> Borrow<CpuCols<T>> for [T]

fn borrow(&self) -> &CpuCols<T>

Immutably borrows from an owned value.

impl<T: Copy> BorrowMut<CpuCols<T>> for [T]

fn borrow_mut(&mut self) -> &mut CpuCols<T>

Mutably borrows from an owned value.

impl<T: Clone + Copy> Clone for CpuCols<T>

fn clone(&self) -> CpuCols<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Copy> Debug for CpuCols<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Default + Copy> Default for CpuCols<T>

fn default() -> CpuCols<T>

Returns the “default value” for a type.

impl<T: Copy + Copy> Copy for CpuCols<T>