#[repr(u8)]pub enum Opcode {
Show 38 variants
ADD = 0,
SUB = 1,
XOR = 2,
OR = 3,
AND = 4,
SLL = 5,
SRL = 6,
SRA = 7,
SLT = 8,
SLTU = 9,
MUL = 10,
MULH = 11,
MULHU = 12,
MULHSU = 13,
DIV = 14,
DIVU = 15,
REM = 16,
REMU = 17,
LB = 18,
LH = 19,
LW = 20,
LBU = 21,
LHU = 22,
SB = 23,
SH = 24,
SW = 25,
BEQ = 26,
BNE = 27,
BLT = 28,
BGE = 29,
BLTU = 30,
BGEU = 31,
JAL = 32,
JALR = 33,
AUIPC = 34,
ECALL = 35,
EBREAK = 36,
UNIMP = 37,
}
Expand description
An opcode (short for “operation code”) specifies the operation to be performed by the processor.
In the context of the RISC-V ISA, an opcode specifies which operation (i.e., addition, subtraction, multiplication, etc.) to perform on up to three operands such as registers, immediates, or memory addresses.
While the SP1 zkVM targets the RISC-V ISA, it uses a custom instruction encoding that uses a different set of opcodes. The main difference is that the SP1 zkVM encodes register operations and immediate operations as the same opcode. For example, the RISC-V opcodes ADD and ADDI both become ADD inside the SP1 zkVM. We utilize flags inside the instruction itself to distinguish between the two.
Refer to the “RV32I Reference Card” here for more details.
Variants§
ADD = 0
rd ← rs1 + rs2, pc ← pc + 4
SUB = 1
rd ← rs1 - rs2, pc ← pc + 4
XOR = 2
rd ← rs1 ^ rs2, pc ← pc + 4
OR = 3
rd ← rs1 | rs2, pc ← pc + 4
AND = 4
rd ← rs1 & rs2, pc ← pc + 4
SLL = 5
rd ← rs1 << rs2, pc ← pc + 4
SRL = 6
rd ← rs1 >> rs2 (logical), pc ← pc + 4
SRA = 7
rd ← rs1 >> rs2 (arithmetic), pc ← pc + 4
SLT = 8
rd ← (rs1 < rs2) ? 1 : 0 (signed), pc ← pc + 4
SLTU = 9
rd ← (rs1 < rs2) ? 1 : 0 (unsigned), pc ← pc + 4
MUL = 10
rd ← rs1 * rs2 (signed), pc ← pc + 4
MULH = 11
rd ← rs1 * rs2 (half), pc ← pc + 4
MULHU = 12
rd ← rs1 * rs2 (half unsigned), pc ← pc + 4
MULHSU = 13
rd ← rs1 * rs2 (half signed unsigned), pc ← pc + 4
DIV = 14
rd ← rs1 / rs2 (signed), pc ← pc + 4
DIVU = 15
rd ← rs1 / rs2 (unsigned), pc ← pc + 4
REM = 16
rd ← rs1 % rs2 (signed), pc ← pc + 4
REMU = 17
rd ← rs1 % rs2 (unsigned), pc ← pc + 4
LB = 18
rd ← sx(m8(rs1 + imm)), pc ← pc + 4
LH = 19
rd ← sx(m16(rs1 + imm)), pc ← pc + 4
LW = 20
rd ← sx(m32(rs1 + imm)), pc ← pc + 4
LBU = 21
rd ← zx(m8(rs1 + imm)), pc ← pc + 4
LHU = 22
rd ← zx(m16(rs1 + imm)), pc ← pc + 4
SB = 23
m8(rs1 + imm) ← rs2[7:0], pc ← pc + 4
SH = 24
m16(rs1 + imm) ← rs2[15:0], pc ← pc + 4
SW = 25
m32(rs1 + imm) ← rs2[31:0], pc ← pc + 4
BEQ = 26
pc ← pc + ((rs1 == rs2) ? imm : 4)
BNE = 27
pc ← pc + ((rs1 != rs2) ? imm : 4)
BLT = 28
pc ← pc + ((rs1 < rs2) ? imm : 4) (signed)
BGE = 29
pc ← pc + ((rs1 >= rs2) ? imm : 4) (signed)
BLTU = 30
pc ← pc + ((rs1 < rs2) ? imm : 4) (unsigned)
BGEU = 31
pc ← pc + ((rs1 >= rs2) ? imm : 4) (unsigned)
JAL = 32
rd ← pc + 4, pc ← pc + imm
JALR = 33
rd ← pc + 4, pc ← (rs1 + imm) & ∼1
AUIPC = 34
rd ← pc + imm, pc ← pc + 4
ECALL = 35
Transfer control to the operating system.
EBREAK = 36
Transfer control to the debugger.
UNIMP = 37
Unimplemented instruction.
Implementations§
Trait Implementations§
Source§impl<'de> Deserialize<'de> for Opcode
impl<'de> Deserialize<'de> for Opcode
Source§fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
Source§impl From<Opcode> for ByteOpcode
impl From<Opcode> for ByteOpcode
Source§impl Ord for Opcode
impl Ord for Opcode
Source§impl PartialOrd for Opcode
impl PartialOrd for Opcode
impl Copy for Opcode
impl Eq for Opcode
impl StructuralPartialEq for Opcode
Auto Trait Implementations§
impl Freeze for Opcode
impl RefUnwindSafe for Opcode
impl Send for Opcode
impl Sync for Opcode
impl Unpin for Opcode
impl UnwindSafe for Opcode
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
Source§impl<T> Downcast for Twhere
T: Any,
impl<T> Downcast for Twhere
T: Any,
Source§fn into_any(self: Box<T>) -> Box<dyn Any>
fn into_any(self: Box<T>) -> Box<dyn Any>
Box<dyn Trait>
(where Trait: Downcast
) to Box<dyn Any>
. Box<dyn Any>
can
then be further downcast
into Box<ConcreteType>
where ConcreteType
implements Trait
.Source§fn into_any_rc(self: Rc<T>) -> Rc<dyn Any>
fn into_any_rc(self: Rc<T>) -> Rc<dyn Any>
Rc<Trait>
(where Trait: Downcast
) to Rc<Any>
. Rc<Any>
can then be
further downcast
into Rc<ConcreteType>
where ConcreteType
implements Trait
.Source§fn as_any(&self) -> &(dyn Any + 'static)
fn as_any(&self) -> &(dyn Any + 'static)
&Trait
(where Trait: Downcast
) to &Any
. This is needed since Rust cannot
generate &Any
’s vtable from &Trait
’s.Source§fn as_any_mut(&mut self) -> &mut (dyn Any + 'static)
fn as_any_mut(&mut self) -> &mut (dyn Any + 'static)
&mut Trait
(where Trait: Downcast
) to &Any
. This is needed since Rust cannot
generate &mut Any
’s vtable from &mut Trait
’s.Source§impl<T> DowncastSync for T
impl<T> DowncastSync for T
Source§impl<Q, K> Equivalent<K> for Q
impl<Q, K> Equivalent<K> for Q
Source§impl<T> Instrument for T
impl<T> Instrument for T
Source§fn instrument(self, span: Span) -> Instrumented<Self>
fn instrument(self, span: Span) -> Instrumented<Self>
Source§fn in_current_span(self) -> Instrumented<Self>
fn in_current_span(self) -> Instrumented<Self>
Source§impl<T> IntoEither for T
impl<T> IntoEither for T
Source§fn into_either(self, into_left: bool) -> Either<Self, Self>
fn into_either(self, into_left: bool) -> Either<Self, Self>
self
into a Left
variant of Either<Self, Self>
if into_left
is true
.
Converts self
into a Right
variant of Either<Self, Self>
otherwise. Read moreSource§fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
self
into a Left
variant of Either<Self, Self>
if into_left(&self)
returns true
.
Converts self
into a Right
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