pub enum RiscvAirId {
Show 45 variants
Cpu = 0,
Program = 1,
ShaExtend = 2,
ShaCompress = 3,
EdAddAssign = 4,
EdDecompress = 5,
Secp256k1Decompress = 6,
Secp256k1AddAssign = 7,
Secp256k1DoubleAssign = 8,
Secp256r1Decompress = 9,
Secp256r1AddAssign = 10,
Secp256r1DoubleAssign = 11,
KeccakPermute = 12,
Bn254AddAssign = 13,
Bn254DoubleAssign = 14,
Bls12381AddAssign = 15,
Bls12381DoubleAssign = 16,
Uint256MulMod = 17,
U256XU2048Mul = 18,
Bls12381FpOpAssign = 19,
Bls12381Fp2AddSubAssign = 20,
Bls12381Fp2MulAssign = 21,
Bn254FpOpAssign = 22,
Bn254Fp2AddSubAssign = 23,
Bn254Fp2MulAssign = 24,
Bls12381Decompress = 25,
SyscallCore = 26,
SyscallPrecompile = 27,
DivRem = 28,
AddSub = 29,
Bitwise = 30,
Mul = 31,
ShiftRight = 32,
ShiftLeft = 33,
Lt = 34,
MemoryInstrs = 35,
Auipc = 36,
Branch = 37,
Jump = 38,
SyscallInstrs = 39,
MemoryGlobalInit = 40,
MemoryGlobalFinalize = 41,
MemoryLocal = 42,
Global = 43,
Byte = 44,
}Expand description
RV32IM AIR Identifiers.
These identifiers are for the various chips in the rv32im prover. We need them in the executor to compute the memory cost of the current shard of execution.
The CoreAirIds are the AIRs that are not part of precompile shards and not the program or
byte AIR.
Variants§
Cpu = 0
The CPU chip.
Program = 1
The program chip.
ShaExtend = 2
The SHA-256 extend chip.
ShaCompress = 3
The SHA-256 compress chip.
EdAddAssign = 4
The Edwards add assign chip.
EdDecompress = 5
The Edwards decompress chip.
Secp256k1Decompress = 6
The secp256k1 decompress chip.
Secp256k1AddAssign = 7
The secp256k1 add assign chip.
Secp256k1DoubleAssign = 8
The secp256k1 double assign chip.
Secp256r1Decompress = 9
The secp256r1 decompress chip.
Secp256r1AddAssign = 10
The secp256r1 add assign chip.
Secp256r1DoubleAssign = 11
The secp256r1 double assign chip.
KeccakPermute = 12
The Keccak permute chip.
Bn254AddAssign = 13
The bn254 add assign chip.
Bn254DoubleAssign = 14
The bn254 double assign chip.
Bls12381AddAssign = 15
The bls12-381 add assign chip.
Bls12381DoubleAssign = 16
The bls12-381 double assign chip.
Uint256MulMod = 17
The uint256 mul mod chip.
U256XU2048Mul = 18
The u256 xu2048 mul chip.
Bls12381FpOpAssign = 19
The bls12-381 fp op assign chip.
Bls12381Fp2AddSubAssign = 20
The bls12-831 fp2 add sub assign chip.
Bls12381Fp2MulAssign = 21
The bls12-831 fp2 mul assign chip.
Bn254FpOpAssign = 22
The bn254 fp2 add sub assign chip.
Bn254Fp2AddSubAssign = 23
The bn254 fp op assign chip.
Bn254Fp2MulAssign = 24
The bn254 fp2 mul assign chip.
Bls12381Decompress = 25
The bls12-381 decompress chip.
SyscallCore = 26
The syscall core chip.
SyscallPrecompile = 27
The syscall precompile chip.
DivRem = 28
The div rem chip.
AddSub = 29
The add sub chip.
Bitwise = 30
The bitwise chip.
Mul = 31
The mul chip.
ShiftRight = 32
The shift right chip.
ShiftLeft = 33
The shift left chip.
Lt = 34
The lt chip.
MemoryInstrs = 35
The memory instructions chip.
Auipc = 36
The auipc chip.
Branch = 37
The branch chip.
Jump = 38
The jump chip.
SyscallInstrs = 39
The syscall instructions chip.
MemoryGlobalInit = 40
The memory global init chip.
MemoryGlobalFinalize = 41
The memory global finalize chip.
MemoryLocal = 42
The memory local chip.
Global = 43
The global chip.
Byte = 44
The byte chip.
Implementations§
Source§impl RiscvAirId
impl RiscvAirId
Sourcepub fn core() -> Vec<RiscvAirId>
pub fn core() -> Vec<RiscvAirId>
Returns the AIRs that are not part of precompile shards and not the program or byte AIR.
Sourcepub fn is_core(self) -> bool
pub fn is_core(self) -> bool
TODO replace these three with subenums or something Whether the ID represents a core AIR.
Sourcepub fn is_precompile(self) -> bool
pub fn is_precompile(self) -> bool
Whether the ID represents a precompile AIR.
Sourcepub fn rows_per_event(&self) -> usize
pub fn rows_per_event(&self) -> usize
The number of rows in the AIR produced by each event.
Trait Implementations§
Source§impl Clone for RiscvAirId
impl Clone for RiscvAirId
Source§fn clone(&self) -> RiscvAirId
fn clone(&self) -> RiscvAirId
1.0.0§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moreSource§impl Debug for RiscvAirId
impl Debug for RiscvAirId
Source§impl<'de> Deserialize<'de> for RiscvAirId
impl<'de> Deserialize<'de> for RiscvAirId
Source§fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
Source§impl Display for RiscvAirId
impl Display for RiscvAirId
Source§impl Enum for RiscvAirId
impl Enum for RiscvAirId
Source§impl<V> EnumArray<V> for RiscvAirId
impl<V> EnumArray<V> for RiscvAirId
Source§impl<'_derivative_strum> From<&'_derivative_strum RiscvAirId> for &'static str
impl<'_derivative_strum> From<&'_derivative_strum RiscvAirId> for &'static str
Source§fn from(x: &'_derivative_strum RiscvAirId) -> &'static str
fn from(x: &'_derivative_strum RiscvAirId) -> &'static str
Source§impl From<CoreAirId> for RiscvAirId
impl From<CoreAirId> for RiscvAirId
Source§impl From<RiscvAirId> for &'static str
impl From<RiscvAirId> for &'static str
Source§fn from(x: RiscvAirId) -> &'static str
fn from(x: RiscvAirId) -> &'static str
Source§impl FromStr for RiscvAirId
impl FromStr for RiscvAirId
Source§impl Hash for RiscvAirId
impl Hash for RiscvAirId
Source§impl IntoEnumIterator for RiscvAirId
impl IntoEnumIterator for RiscvAirId
type Iterator = RiscvAirIdIter
fn iter() -> RiscvAirIdIter ⓘ
Source§impl Ord for RiscvAirId
impl Ord for RiscvAirId
Source§impl PartialEq<CoreAirId> for RiscvAirId
impl PartialEq<CoreAirId> for RiscvAirId
Source§impl PartialEq<RiscvAirId> for CoreAirId
impl PartialEq<RiscvAirId> for CoreAirId
Source§impl PartialEq for RiscvAirId
impl PartialEq for RiscvAirId
Source§impl PartialOrd for RiscvAirId
impl PartialOrd for RiscvAirId
Source§impl Serialize for RiscvAirId
impl Serialize for RiscvAirId
Source§impl TryFrom<RiscvAirId> for CoreAirId
impl TryFrom<RiscvAirId> for CoreAirId
Source§type Error = CoreAirIdConvertError
type Error = CoreAirIdConvertError
Source§fn try_from(
parent: RiscvAirId,
) -> Result<Self, <Self as TryFrom<RiscvAirId>>::Error>
fn try_from( parent: RiscvAirId, ) -> Result<Self, <Self as TryFrom<RiscvAirId>>::Error>
impl Copy for RiscvAirId
impl Eq for RiscvAirId
impl StructuralPartialEq for RiscvAirId
Auto Trait Implementations§
impl Freeze for RiscvAirId
impl RefUnwindSafe for RiscvAirId
impl Send for RiscvAirId
impl Sync for RiscvAirId
impl Unpin for RiscvAirId
impl UnwindSafe for RiscvAirId
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Source§fn into_either(self, into_left: bool) -> Either<Self, Self>
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self into a Left variant of Either<Self, Self>
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fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
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