pub struct Core {Show 154 fields
pub PC: xlenbits,
pub nextPC: xlenbits,
pub x1: regtype,
pub x2: regtype,
pub x3: regtype,
pub x4: regtype,
pub x5: regtype,
pub x6: regtype,
pub x7: regtype,
pub x8: regtype,
pub x9: regtype,
pub x10: regtype,
pub x11: regtype,
pub x12: regtype,
pub x13: regtype,
pub x14: regtype,
pub x15: regtype,
pub x16: regtype,
pub x17: regtype,
pub x18: regtype,
pub x19: regtype,
pub x20: regtype,
pub x21: regtype,
pub x22: regtype,
pub x23: regtype,
pub x24: regtype,
pub x25: regtype,
pub x26: regtype,
pub x27: regtype,
pub x28: regtype,
pub x29: regtype,
pub x30: regtype,
pub x31: regtype,
pub cur_privilege: Privilege,
pub cur_inst: xlenbits,
pub misa: Misa,
pub mstatus: Mstatus,
pub menvcfg: MEnvcfg,
pub senvcfg: SEnvcfg,
pub mie: Minterrupts,
pub mip: Minterrupts,
pub medeleg: Medeleg,
pub mideleg: Minterrupts,
pub mtvec: Mtvec,
pub mcause: Mcause,
pub mepc: xlenbits,
pub mtval: xlenbits,
pub mscratch: xlenbits,
pub scounteren: Counteren,
pub mcounteren: Counteren,
pub mcountinhibit: Counterin,
pub mcycle: BitVector<64>,
pub mtime: BitVector<64>,
pub minstret: BitVector<64>,
pub minstret_increment: bool,
pub mvendorid: BitVector<32>,
pub mimpid: xlenbits,
pub marchid: xlenbits,
pub mhartid: xlenbits,
pub mconfigptr: xlenbits,
pub stvec: Mtvec,
pub sscratch: xlenbits,
pub sepc: xlenbits,
pub scause: Mcause,
pub stval: xlenbits,
pub tselect: xlenbits,
pub vstart: BitVector<16>,
pub vl: xlenbits,
pub vtype: Vtype,
pub pmpcfg_n: [Pmpcfg_ent; 64],
pub pmpaddr_n: [xlenbits; 64],
pub vr0: vregtype,
pub vr1: vregtype,
pub vr2: vregtype,
pub vr3: vregtype,
pub vr4: vregtype,
pub vr5: vregtype,
pub vr6: vregtype,
pub vr7: vregtype,
pub vr8: vregtype,
pub vr9: vregtype,
pub vr10: vregtype,
pub vr11: vregtype,
pub vr12: vregtype,
pub vr13: vregtype,
pub vr14: vregtype,
pub vr15: vregtype,
pub vr16: vregtype,
pub vr17: vregtype,
pub vr18: vregtype,
pub vr19: vregtype,
pub vr20: vregtype,
pub vr21: vregtype,
pub vr22: vregtype,
pub vr23: vregtype,
pub vr24: vregtype,
pub vr25: vregtype,
pub vr26: vregtype,
pub vr27: vregtype,
pub vr28: vregtype,
pub vr29: vregtype,
pub vr30: vregtype,
pub vr31: vregtype,
pub vcsr: Vcsr,
pub mhpmevent: [HpmEvent; 32],
pub mhpmcounter: [BitVector<64>; 32],
pub float_result: BitVector<64>,
pub float_fflags: BitVector<64>,
pub f0: fregtype,
pub f1: fregtype,
pub f2: fregtype,
pub f3: fregtype,
pub f4: fregtype,
pub f5: fregtype,
pub f6: fregtype,
pub f7: fregtype,
pub f8: fregtype,
pub f9: fregtype,
pub f10: fregtype,
pub f11: fregtype,
pub f12: fregtype,
pub f13: fregtype,
pub f14: fregtype,
pub f15: fregtype,
pub f16: fregtype,
pub f17: fregtype,
pub f18: fregtype,
pub f19: fregtype,
pub f20: fregtype,
pub f21: fregtype,
pub f22: fregtype,
pub f23: fregtype,
pub f24: fregtype,
pub f25: fregtype,
pub f26: fregtype,
pub f27: fregtype,
pub f28: fregtype,
pub f29: fregtype,
pub f30: fregtype,
pub f31: fregtype,
pub fcsr: Fcsr,
pub mcyclecfg: CountSmcntrpmf,
pub minstretcfg: CountSmcntrpmf,
pub mtimecmp: BitVector<64>,
pub stimecmp: BitVector<64>,
pub htif_tohost: BitVector<64>,
pub htif_done: bool,
pub htif_exit_code: BitVector<64>,
pub htif_cmd_write: bool,
pub htif_payload_writes: BitVector<4>,
pub tlb: [Option<TLB_Entry>; 64],
pub satp: xlenbits,
pub hart_state: HartState,
pub config: Config,
}Expand description
The software core.
This struct represents a software core, and holds all the registers as well as the core configuration. The core is the main abstraction exposed by the softcore library and represents a single execution thread.
The raw functions translated directly from the specification are available in the raw module, whereas higher-level wrappers are implemented as methods on the Core struct directly.
Fields§
§PC: xlenbits§nextPC: xlenbits§x1: regtype§x2: regtype§x3: regtype§x4: regtype§x5: regtype§x6: regtype§x7: regtype§x8: regtype§x9: regtype§x10: regtype§x11: regtype§x12: regtype§x13: regtype§x14: regtype§x15: regtype§x16: regtype§x17: regtype§x18: regtype§x19: regtype§x20: regtype§x21: regtype§x22: regtype§x23: regtype§x24: regtype§x25: regtype§x26: regtype§x27: regtype§x28: regtype§x29: regtype§x30: regtype§x31: regtype§cur_privilege: Privilege§cur_inst: xlenbits§misa: Misa§mstatus: Mstatus§menvcfg: MEnvcfg§senvcfg: SEnvcfg§mie: Minterrupts§mip: Minterrupts§medeleg: Medeleg§mideleg: Minterrupts§mtvec: Mtvec§mcause: Mcause§mepc: xlenbits§mtval: xlenbits§mscratch: xlenbits§scounteren: Counteren§mcounteren: Counteren§mcountinhibit: Counterin§mcycle: BitVector<64>§mtime: BitVector<64>§minstret: BitVector<64>§minstret_increment: bool§mvendorid: BitVector<32>§mimpid: xlenbits§marchid: xlenbits§mhartid: xlenbits§mconfigptr: xlenbits§stvec: Mtvec§sscratch: xlenbits§sepc: xlenbits§scause: Mcause§stval: xlenbits§tselect: xlenbits§vstart: BitVector<16>§vl: xlenbits§vtype: Vtype§pmpcfg_n: [Pmpcfg_ent; 64]§pmpaddr_n: [xlenbits; 64]§vr0: vregtype§vr1: vregtype§vr2: vregtype§vr3: vregtype§vr4: vregtype§vr5: vregtype§vr6: vregtype§vr7: vregtype§vr8: vregtype§vr9: vregtype§vr10: vregtype§vr11: vregtype§vr12: vregtype§vr13: vregtype§vr14: vregtype§vr15: vregtype§vr16: vregtype§vr17: vregtype§vr18: vregtype§vr19: vregtype§vr20: vregtype§vr21: vregtype§vr22: vregtype§vr23: vregtype§vr24: vregtype§vr25: vregtype§vr26: vregtype§vr27: vregtype§vr28: vregtype§vr29: vregtype§vr30: vregtype§vr31: vregtype§vcsr: Vcsr§mhpmevent: [HpmEvent; 32]§mhpmcounter: [BitVector<64>; 32]§float_result: BitVector<64>§float_fflags: BitVector<64>§f0: fregtype§f1: fregtype§f2: fregtype§f3: fregtype§f4: fregtype§f5: fregtype§f6: fregtype§f7: fregtype§f8: fregtype§f9: fregtype§f10: fregtype§f11: fregtype§f12: fregtype§f13: fregtype§f14: fregtype§f15: fregtype§f16: fregtype§f17: fregtype§f18: fregtype§f19: fregtype§f20: fregtype§f21: fregtype§f22: fregtype§f23: fregtype§f24: fregtype§f25: fregtype§f26: fregtype§f27: fregtype§f28: fregtype§f29: fregtype§f30: fregtype§f31: fregtype§fcsr: Fcsr§mcyclecfg: CountSmcntrpmf§minstretcfg: CountSmcntrpmf§mtimecmp: BitVector<64>§stimecmp: BitVector<64>§htif_tohost: BitVector<64>§htif_done: bool§htif_exit_code: BitVector<64>§htif_cmd_write: bool§htif_payload_writes: BitVector<4>§tlb: [Option<TLB_Entry>; 64]§satp: xlenbits§hart_state: HartState§config: ConfigImplementations§
Source§impl Core
impl Core
Sourcepub fn reset(&mut self)
pub fn reset(&mut self)
Reset the core, initializing registers with specified reset values.
This does not reset all registers and CSRs of the core, it only performs the minimal reset required by the specification.
This function should be called on a fresh core to ensure the core starts in a sensible state.
Sourcepub fn get(&mut self, reg: GeneralRegister) -> u64
pub fn get(&mut self, reg: GeneralRegister) -> u64
Get the value of a general purpose register.
Sourcepub fn set(&mut self, reg: GeneralRegister, value: u64)
pub fn set(&mut self, reg: GeneralRegister, value: u64)
Set the value of a general purpose register.
Sourcepub fn get_csr(&mut self, csr: u64) -> Option<u64>
pub fn get_csr(&mut self, csr: u64) -> Option<u64>
Get the value of a CSR identified by its CSR index.
This function returns None if the CSR can not be read by the current privilege level or is not implemented given the core configuration.
Sourcepub fn set_csr(&mut self, csr: u64, value: u64) -> Option<u64>
pub fn set_csr(&mut self, csr: u64, value: u64) -> Option<u64>
Set the value of a CSR identified by its CSR index.
This function returns None if the CSR can not be written by the current privilege level or is not implemented given the core configuration. Otherwise the new CSR value is returned.
Sourcepub fn csrrw(
&mut self,
rd: GeneralRegister,
csr: u64,
rs1: GeneralRegister,
) -> Result<(), ExecutionResult>
pub fn csrrw( &mut self, rd: GeneralRegister, csr: u64, rs1: GeneralRegister, ) -> Result<(), ExecutionResult>
Atomic Read and Write CSR
This function has the same effect as executing the CSRRW instruction, except for moving
the PC on success and trapping on failure.
Sourcepub fn csrrs(
&mut self,
rd: GeneralRegister,
csr: u64,
rs1: GeneralRegister,
) -> Result<(), ExecutionResult>
pub fn csrrs( &mut self, rd: GeneralRegister, csr: u64, rs1: GeneralRegister, ) -> Result<(), ExecutionResult>
Atomic Read and Set bits CSR
This function has the same effect as executing the CSRRS instruction, except for moving
the PC on success and trapping on failure.
Sourcepub fn csrrc(
&mut self,
rd: GeneralRegister,
csr: u64,
rs1: GeneralRegister,
) -> Result<(), ExecutionResult>
pub fn csrrc( &mut self, rd: GeneralRegister, csr: u64, rs1: GeneralRegister, ) -> Result<(), ExecutionResult>
Atomic Read and Clear bits CSR
This function has the same effect as executing the CSRRc instruction, except for moving
the PC on success and trapping on failure.
Sourcepub fn csrrwi(
&mut self,
rd: GeneralRegister,
csr: u64,
uimm: u64,
) -> Result<(), ExecutionResult>
pub fn csrrwi( &mut self, rd: GeneralRegister, csr: u64, uimm: u64, ) -> Result<(), ExecutionResult>
Atomic Read and Write immediate CSR
This function has the same effect as executing the CSRRWI instruction, except for moving
the PC on success and trapping on failure.
Sourcepub fn csrrsi(
&mut self,
rd: GeneralRegister,
csr: u64,
uimm: u64,
) -> Result<(), ExecutionResult>
pub fn csrrsi( &mut self, rd: GeneralRegister, csr: u64, uimm: u64, ) -> Result<(), ExecutionResult>
Atomic Read and Set bits immediate CSR
This function has the same effect as executing the CSRRSI instruction, except for moving
the PC on success and trapping on failure.
Sourcepub fn csrrci(
&mut self,
rd: GeneralRegister,
csr: u64,
uimm: u64,
) -> Result<(), ExecutionResult>
pub fn csrrci( &mut self, rd: GeneralRegister, csr: u64, uimm: u64, ) -> Result<(), ExecutionResult>
Atomic Read and Clear bits immediate CSR
This function has the same effect as executing the CSRRCI instruction, except for moving
the PC on success and trapping on failure.
Sourcepub fn decode_instr(&mut self, instr: u32) -> ast
pub fn decode_instr(&mut self, instr: u32) -> ast
Decode an instruction
Sourcepub fn encode_instr(&mut self, instr: ast) -> u32
pub fn encode_instr(&mut self, instr: ast) -> u32
Encode and instruction
Sourcepub fn is_csr_defined(&mut self, csr_id: usize) -> bool
pub fn is_csr_defined(&mut self, csr_id: usize) -> bool
Return true if the CSR is defined (and enabled) on the core
Sourcepub fn dispatch_interrupt(&mut self)
pub fn dispatch_interrupt(&mut self)
Dispatch pending interrupt
This function looks for pending and enabled interrupts and perform the dispatch for the interrupt with highest priority.
Sourcepub fn inject_exception(&mut self, exception: ExceptionType, tval: u64)
pub fn inject_exception(&mut self, exception: ExceptionType, tval: u64)
Inject an exception, triggerring the appropriate trap handler
The target privilege mode depends on the current execution mode and the *deleg CSR
registers.
The tval is the trap value, which depends on the exception type. Memory access fault will
usually provide the faulting address.
Sourcepub fn get_pmpaddr(&self, index: usize) -> u64
pub fn get_pmpaddr(&self, index: usize) -> u64
Return the pmpaddr<index> register.
Sourcepub fn set_pmpaddr(&mut self, index: usize, val: u64)
pub fn set_pmpaddr(&mut self, index: usize, val: u64)
Set the pmpaddr<index> register to the given value.
Sourcepub fn set_pmpcfg(&mut self, index: usize, val: u64)
pub fn set_pmpcfg(&mut self, index: usize, val: u64)
Set the pmpcfg<index> register to the given value.
Sourcepub fn pmp_check(
&mut self,
addr: u64,
access_kind: AccessType<()>,
) -> Option<ExceptionType>
pub fn pmp_check( &mut self, addr: u64, access_kind: AccessType<()>, ) -> Option<ExceptionType>
Check if an 8 byte access is allowed with the current mode and PMP configuration.
Return None is the check succeed, or an error otherwise.