Struct smbioslib::SMBiosProcessorInformation[][src]

pub struct SMBiosProcessorInformation<'a> { /* fields omitted */ }
Expand description

Processor Information (Type 4)

The information in this structure defines the attributes of a single processor; a separate structure instance is provided for each system processor socket/slot. For example, a system with an IntelDX2™ processor would have a single structure instance while a system with an IntelSX2™ processor would have a structure to describe the main CPU and a second structure to describe the 80487 co1021 processor.

NOTE One structure is provided for each processor instance in a system. For example, a system that supports up to two processors includes two Processor Information structures — even if only one processor is currently installed. Software that interprets the SMBIOS information can count the Processor Information structures to determine the maximum possible configuration of the system.

Compliant with: DMTF SMBIOS Reference Specification 3.4.0 (DSP0134) Document Date: 2020-07-17

Implementations

Socket reference designation

EXAMPLE: “J202”

Processor type

Processor family

Processor manufacturer

Raw processor identification data

Processor version

Voltage

External clock frequency, in MHz

If the value is unknown, the field is set to 0.

Maximum processor speed (in MHz) supported by the system for this processor socket

0E9h is for a 233 MHz processor.

NOTE: This field identifies a capability for the system, not the processor itself.

Current speed

Same format as Max Speed

NOTE: This field identifies the processor’s speed at system boot; the processor may support more than one speed.

Status bit field

Processor upgrade

Handle of a [SMBiosCacheInformation] structure that defines the attributes of the primary (Level 1) cache for this processor

For version 2.1 and version 2.2 implementations, the value is 0FFFFh if the processor has no L1 cache. For version 2.3 and later implementations, the value is 0FFFFh if the Cache Information structure is not provided.

Handle of a [SMBiosCacheInformation] structure that defines the attributes of the primary (Level 2) cache for this processor

For version 2.1 and version 2.2 implementations, the value is 0FFFFh if the processor has no L2 cache. For version 2.3 and later implementations, the value is 0FFFFh if the Cache Information structure is not provided.

Handle of a [SMBiosCacheInformation] structure that defines the attributes of the primary (Level 3) cache for this processor

For version 2.1 and version 2.2 implementations, the value is 0FFFFh if the processor has no L3 cache. For version 2.3 and later implementations, the value is 0FFFFh if the Cache Information structure is not provided.

The serial number of this processor

This value is set by the manufacturer and normally not changeable.

The asset tag of this processor

The part number of this processor

This value is set by the manufacturer and normally not changeable.

Number of cores per processor socket

For core counts of 256 or greater, the ‘core_count_2’ field is set to the number of cores.

Number of enabled cores per processor socket

For core counts of 256 or greater, the ‘cores_enabled_2’ field is set to the number of enabled cores.

Number of threads per processor socket

For thread counts of 256 or greater, ‘thread_count_2’ field is set to the number of threads.

Defines which functions the processor supports

Processor family 2

Number of Cores per processor socket.

Supports core counts >255. If this field is present, it holds the core count for the processor socket. ‘core_count’ will also hold the core count, except for core counts that are 256 or greater. In that case, ‘core_count’ shall be set to ‘CoreCount::SeeCoreCount2’ and ‘core_count_2’ will hold the count.

Number of enabled cores per processor socket.

Supports core enabled counts >255. If this field is present, it holds the core enabled count for the processor socket. ‘cores_enabled’ will also hold the core enabled count, except for core counts that are 256 or greater. In that case, ‘cores_enabled’ shall be set to ‘CoresEnabled::SeeCoresEnabled2’ and ‘cores_enabled_2’ will hold the count.

Number of threads per processor socket.

Supports thread counts >255. If this field is present, it holds the thread count for the processor socket. ‘thread_count’ will also hold the thread count, except for thread counts that are 256 or greater. In that case, ‘thread_count’ shall be set to ‘ThreadCount::SeeThreadCount2’ and ‘thread_count_2’ will hold the count.

Trait Implementations

Formats the value using the given formatter. Read more

The SMBIOS structure type Read more

Creates a new instance of the implementing SMBIOS type

Contains the standard parts/sections of the implementing SMBIOS type.

Serialize this value into the given Serde serializer. Read more

Auto Trait Implementations

Blanket Implementations

Gets the TypeId of self. Read more

Immutably borrows from an owned value. Read more

Mutably borrows from an owned value. Read more

Performs the conversion.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.