Struct smbioslib::SMBiosCacheInformation [−][src]
pub struct SMBiosCacheInformation<'a> { /* fields omitted */ }
Expand description
Cache Information (Type 7)
This structure defines the attributes of CPU cache device in the system. One structure is specified for each such device, whether the device is internal to or external to the CPU module. Cache modules can be associated with a processor structure in one or two ways depending on the SMBIOS version
Compliant with: DMTF SMBIOS Reference Specification 3.4.0 (DSP0134) Document Date: 2020-07-17
Implementations
String number for reference designation
Bit fields describing the cache configuration
Maximum size that can be installed
Same format as Max Cache Size field; set to 0 if no cache is installed
Supported SRAM type
Current SRAM type
Cache module speed, in nanoseconds. The value is 0 if the speed is unknown.
Error-correction scheme supported by this cache component
Logical type of cache
Associativity of the cache
Maximum cache size
Installed cache size
Trait Implementations
The SMBIOS structure type Read more
Creates a new instance of the implementing SMBIOS type
Contains the standard parts/sections of the implementing SMBIOS type.
Auto Trait Implementations
impl<'a> RefUnwindSafe for SMBiosCacheInformation<'a>
impl<'a> Send for SMBiosCacheInformation<'a>
impl<'a> Sync for SMBiosCacheInformation<'a>
impl<'a> Unpin for SMBiosCacheInformation<'a>
impl<'a> UnwindSafe for SMBiosCacheInformation<'a>