Struct shift_register_driver::sipo::ShiftRegister40 [−][src]
pub struct ShiftRegister40<Pin1, Pin2, Pin3> where
Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin, { /* fields omitted */ }Serial-in parallel-out shift register
Methods
impl<Pin1, Pin2, Pin3> ShiftRegister40<Pin1, Pin2, Pin3> where
Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin, [src]
impl<Pin1, Pin2, Pin3> ShiftRegister40<Pin1, Pin2, Pin3> where
Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin, pub fn new(clock: Pin1, latch: Pin2, data: Pin3) -> Self[src]
pub fn new(clock: Pin1, latch: Pin2, data: Pin3) -> SelfCreates a new SIPO shift register from clock, latch, and data output pins
pub fn decompose(&self) -> [ShiftRegisterPin; 40][src]
pub fn decompose(&self) -> [ShiftRegisterPin; 40]Get embedded-hal output pins to control the shift register outputs
pub fn release(self) -> (Pin1, Pin2, Pin3)[src]
pub fn release(self) -> (Pin1, Pin2, Pin3)Consume the shift register and return the original clock, latch, and data output pins
Auto Trait Implementations
impl<Pin1, Pin2, Pin3> Send for ShiftRegister40<Pin1, Pin2, Pin3> where
Pin1: Send,
Pin2: Send,
Pin3: Send,
impl<Pin1, Pin2, Pin3> Send for ShiftRegister40<Pin1, Pin2, Pin3> where
Pin1: Send,
Pin2: Send,
Pin3: Send, impl<Pin1, Pin2, Pin3> !Sync for ShiftRegister40<Pin1, Pin2, Pin3>
impl<Pin1, Pin2, Pin3> !Sync for ShiftRegister40<Pin1, Pin2, Pin3>