Type Alias W 

pub type W = W<TopCtrlSpec>;

Register TOP_CTRL writer

Aliased Type

pub struct W { /* private fields */ }

Implementations

impl W

pub fn sse(&mut self) -> SseW<'_, TopCtrlSpec>

Bit 0 - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled

pub fn frf(&mut self) -> FrfW<'_, TopCtrlSpec>

Bits 1:2 - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)

pub fn sclkdir(&mut self) -> SclkdirW<'_, TopCtrlSpec>

Bit 3 - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx

pub fn sfrmdir(&mut self) -> SfrmdirW<'_, TopCtrlSpec>

Bit 4 - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx

pub fn dss(&mut self) -> DssW<'_, TopCtrlSpec>

Bits 5:9 - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits

pub fn spo(&mut self) -> SpoW<'_, TopCtrlSpec>

Bit 10 - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high

pub fn sph(&mut self) -> SphW<'_, TopCtrlSpec>

Bit 11 - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame

pub fn rsvd2(&mut self) -> Rsvd2W<'_, TopCtrlSpec>

Bit 12

pub fn trail(&mut self) -> TrailW<'_, TopCtrlSpec>

Bit 13 - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts

pub fn hold_frame_low(&mut self) -> HoldFrameLowW<'_, TopCtrlSpec>

Bit 14 - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there’s no bit clock, or the data transfers before the stop clock will be discarded.

pub fn ifs(&mut self) -> IfsW<'_, TopCtrlSpec>

Bit 15 - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)

pub fn scfr(&mut self) -> ScfrW<'_, TopCtrlSpec>

Bit 16 - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers.

pub fn tte(&mut self) -> TteW<'_, TopCtrlSpec>

Bit 17 - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data

pub fn ttelp(&mut self) -> TtelpW<'_, TopCtrlSpec>

Bit 18 - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB

pub fn rsvd(&mut self) -> RsvdW<'_, TopCtrlSpec>

Bits 19:31