pub type W = W<DebugLoopSpec>;Expand description
Register DEBUG_LOOP writer
Aliased Type§
pub struct W { /* private fields */ }Implementations§
Source§impl W
impl W
Sourcepub fn da2ad_loop_back(&mut self) -> Da2adLoopBackW<'_, DebugLoopSpec>
pub fn da2ad_loop_back(&mut self) -> Da2adLoopBackW<'_, DebugLoopSpec>
Bit 0 - TX–>RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI
Sourcepub fn ad2da_loop_back(&mut self) -> Ad2daLoopBackW<'_, DebugLoopSpec>
pub fn ad2da_loop_back(&mut self) -> Ad2daLoopBackW<'_, DebugLoopSpec>
Bit 1 - RX–>TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input
Sourcepub fn sp_clk_sel(&mut self) -> SpClkSelW<'_, DebugLoopSpec>
pub fn sp_clk_sel(&mut self) -> SpClkSelW<'_, DebugLoopSpec>
Bit 2 - clock select 0: xtal clock 1: pll clock
Sourcepub fn rsvd3(&mut self) -> Rsvd3W<'_, DebugLoopSpec>
pub fn rsvd3(&mut self) -> Rsvd3W<'_, DebugLoopSpec>
Bits 3:7
Sourcepub fn sp_clk_div_update(&mut self) -> SpClkDivUpdateW<'_, DebugLoopSpec>
pub fn sp_clk_div_update(&mut self) -> SpClkDivUpdateW<'_, DebugLoopSpec>
Bit 8 - update sp clock divider
Sourcepub fn rsvd2(&mut self) -> Rsvd2W<'_, DebugLoopSpec>
pub fn rsvd2(&mut self) -> Rsvd2W<'_, DebugLoopSpec>
Bits 9:15
Sourcepub fn sp_clk_div(&mut self) -> SpClkDivW<'_, DebugLoopSpec>
pub fn sp_clk_div(&mut self) -> SpClkDivW<'_, DebugLoopSpec>
Bits 16:23 - sp clock divider value
Sourcepub fn rsvd(&mut self) -> RsvdW<'_, DebugLoopSpec>
pub fn rsvd(&mut self) -> RsvdW<'_, DebugLoopSpec>
Bits 24:31