Module status 

Status Register

Structs

StatusSpec

Status Register

Type Aliases

BceR

Field BCE reader - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero

BceW

Field BCE writer - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero

BsyR

Field BSY reader - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data

BsyW

Field BSY writer - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data

CssR

Field CSS reader - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals

CssW

Field CSS writer - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals

EocR

Field EOC reader - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition

EocW

Field EOC writer - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition

OssR

Field OSS reader - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO.

OssW

Field OSS writer - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO.

PintR

Field PINT reader - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending

PintW

Field PINT writer - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending

R

Register STATUS reader

RflR

Field RFL reader - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field.

RflW

Field RFL writer - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field.

RfsR

Field RFS reader - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request

RfsW

Field RFS writer - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request

RneR

Field RNE reader - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty

RneW

Field RNE writer - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty

RorR

Field ROR reader - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request

RorW

Field ROR writer - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request

Rsvd2R

Field RSVD2 reader -

Rsvd2W

Field RSVD2 writer -

Rsvd3R

Field RSVD3 reader -

Rsvd3W

Field RSVD3 writer -

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

TflR

Field TFL reader - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field.

TflW

Field TFL writer - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field.

TfsR

Field TFS reader - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request

TfsW

Field TFS writer - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request

TintR

Field TINT reader - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request

TintW

Field TINT writer - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request

TnfR

Field TNF reader - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full

TnfW

Field TNF writer - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full

TurR

Field TUR reader - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)

TurW

Field TUR writer - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)

TxOssR

Field TX_OSS reader - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero.

TxOssW

Field TX_OSS writer - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero.

W

Register STATUS writer