Type Alias R 

pub type R = R<StatusSpec>;

Register STATUS reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn bsy(&self) -> BsyR

Bit 0 - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data

pub fn css(&self) -> CssR

Bit 1 - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals

pub fn pint(&self) -> PintR

Bit 2 - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending

pub fn tint(&self) -> TintR

Bit 3 - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request

pub fn eoc(&self) -> EocR

Bit 4 - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition

pub fn tfs(&self) -> TfsR

Bit 5 - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request

pub fn tnf(&self) -> TnfR

Bit 6 - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full

pub fn tfl(&self) -> TflR

Bits 7:10 - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field.

pub fn rsvd3(&self) -> Rsvd3R

Bit 11

pub fn tur(&self) -> TurR

Bit 12 - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)

pub fn rfs(&self) -> RfsR

Bit 13 - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request

pub fn rne(&self) -> RneR

Bit 14 - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty

pub fn rfl(&self) -> RflR

Bits 15:18 - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field.

pub fn rsvd2(&self) -> Rsvd2R

Bit 19

pub fn ror(&self) -> RorR

Bit 20 - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request

pub fn bce(&self) -> BceR

Bit 21 - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero

pub fn tx_oss(&self) -> TxOssR

Bit 22 - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero.

pub fn oss(&self) -> OssR

Bit 23 - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO.

pub fn rsvd(&self) -> RsvdR

Bits 24:31